ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors

It is challenging to manage the thermal behavior of many-core microprocessors while still keeping them running at high performance since the control... (more)

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip

Digital (droplet-based) microfluidic technology offers an attractive platform for implementing a wide variety of biochemical laboratory protocols,... (more)

State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers

The logic synthesis of ultra-high-speed FSMs is presented. The state assignment is based on a well-known method that uses output vectors. This... (more)

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Multicore processors have proliferated several domains ranging from small-scale embedded systems to large data centers, making tiled CMPs (TCMPs) the... (more)

Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization

As finite energy resources are being consumed at faster rate than they can be replaced, renewable energy resources have drawn extensive attention.... (more)

Hardware Trojans

Given the increasing complexity of modern electronics and the cost of fabrication, entities from around the globe have become more heavily involved in all phases of the electronics supply chain. In this environment, hardware Trojans (i.e., malicious modifications or inclusions made by untrusted third parties) pose major security concerns,... (more)

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests

This article describes a procedure for test data compression targeting functional and partially... (more)

Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor

For decades, various concepts in security monitoring have been proposed. In principle, they all in common in regard to the monitoring of the execution... (more)

Improving PCM Endurance with a Constant-Cost Wear Leveling Design

Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling (WL)... (more)

Ripple 2.0

Routability is one of the most important problems in high-performance circuit designs. From the viewpoint of placement design, two major factors cause routing congestion: (i) interconnections between cells and (ii) connections on macro blockages. In this article, we present a routability-driven placer, Ripple 2.0, which emphasizes both kinds of... (more)

A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities

In this article, we present a compact implementation of the Salsa20 stream cipher that is targeted towards lightweight cryptographic devices such as... (more)

Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures

Scratchpad memory (SPM) is considered a useful component in the memory hierarchy, solely or along... (more)


Best Paper Award: Congratulations to Chung-Wei Lin, Bowen Zheng, Qi Zhu, and Alberto Sangiovanni-Vincentelli on receiving the 2016 ACM TODAES Best Paper Award for their article titled Security-Aware Design Methodology and Optimization for Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1, Article 18, November 2015.

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

Forthcoming Articles
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), the on-chip networks are facing serious challenges in providing fast communication for various tasks and cores. One promising on-chip network design shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behav-iors, both of which have not been fully exploited in existing mapping algorithms. In this paper, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened but-terfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

An Elastic Mixed-Criticality Task Model and Early-Release EDF Scheduling Algorithms

Most existing MC scheduling algorithms guarantee timely executions of high-criticality (HC) tasks at the expense of discarding low-criticality (LC) tasks, which can cause serious service interruption for such tasks. In this work, aiming at providing guaranteed services for LC tasks, we study an Elastic Mixed-Criticality (E-MC) task model for dual-criticality systems. Specifically, the model allows each LC task to specify its maximum period (i.e., minimum service level) and a set of early-release points. We propose an Early-Release (ER) mechanism that enables LC tasks be released more frequently and thus improve their service levels at runtime, with both conservative and aggressive approaches to exploiting system slack being considered, which is applied to both EDF and preference-oriented earliest-deadline (POED) schedulers. We formally prove the correctness of the proposed ER-EDF scheduler on guaranteeing the timeliness of all tasks through judicious management of the early releases of LC tasks. The proposed model and schedulers are evaluated through extensive simulations. The results show that, by moderately relaxing the service requirements of LC tasks in MC task sets (i.e., by having LC tasks maximum periods in the E-MC model be 2 to 3 times of their desired MC periods), most transformed E-MC task sets can be successfully scheduled without sacrificing the timeliness of HC tasks. Moreover, with the proposed ER mechanism, the runtime performance of tasks (e.g., execution frequencies of LC tasks, response times and jitters of HC tasks) can be significantly improved under the ER schedulers when compared to that of the state-of-the-art EDF-VD scheduler.

On the Restore Time Variations of Future DRAM Memory

As the de facto main memory standard, DRAM has achieved dramatic density improvement in the past four decades, along with the advancements in process technology. Recent studies reveal that one of the major challenges in scaling DRAM into deep sub-micron regime is its significant variations on cell restore time, which affect timing constraints such as write recovery time tWR. Adopting traditional approaches results in either low yield rate or large performance degradation. In this paper, we propose schemes to expose the variations to the architectural level. By constructing memory chunks with different access speeds and, in particular, exploiting the performance benefits of fast chunks, a variation-aware memory controller can effectively mitigate the performance loss due to relaxed timing constraints. We then proposed restore time aware rank construction and page allocation schemes to make better use of fast chunks. Our experimental results show that, comparing to traditional designs such as row sparing and ECC, the proposed schemes help to improve system performance by about 16% and 20%, respectively, for 20nm and 14nm technology nodes on a four-core multiprocessor system.

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration

Flash memory is widely used in mobile phones to store contact information, applications files and other types of data. In an operating system, the buffer cache keeps the I/O blocks in DRAM to reduce the slow flash accesses. However, in smartphones, we observed two issues which reduce the benefits of the buffer cache. First, the bulk of synchronous writes frequently force the data being written to flash due to the reliability issues. Second, the large amount of I/O accesses from background applications diminishes the buffer cache efficiency of the foreground application, which degrades the user experience. In this paper, we propose a buffer cache architecture with hybrid DRAM/PCM memory, which improves the I/O performance and user experience for smartphones. We use a DRAM first-level buffer cache to provide high buffer cache performance and a PCM last-level buffer cache to reduce the impact of frequent synchronous writes. Based on the proposed hierarchical buffer cache architecture, we propose a sub-block management and background flush to reduce the impact of the PCM write limitation and the dirty block write-back overhead, respectively. To improve the user experience, we propose a Least-Recently-Activated first replacement policy (LRA) to keep the data from the applications that are most likely to become the foreground one. The experimental results show that with the proposed mechanisms, our hierarchical buffer cache can improve the I/O response time by 20% compared to the conventional buffer cache. The proposed LRA can improve the foreground application performance by 1.74x compared to the conventional CLOCK policy.

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems

During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of non-volatile flash in the systems memory hierarchy. The increasing capacity of NAND flash memory introduces large RAMfootprint to store the logical to physical address mapping. The demand-based approach can effectively reduce and well control the RAM footprint. However, extra address translation overhead is also introduced which may degrade the system performance. In this paper, we present CDFTL, an adaptive Caching mechanism for Demand-based Flash Translation Layer, for NAND flash memory storage systems. CDFTL adopts both the fine-grained entry-based caching mechanismto exploit temporal locality and the coarse-grained translation-page-based cachingmechanism to exploit spatial locality of workloads. By selectively caching the on-demand address mappings and adaptively changing the space configurations of two granularities, CDFTL can effectively utilize the RAM space and improve the cache hit ratio. We evaluate CDFTL under a real hardware embedded platform using a variety of I/O traces. Experimental results show that our technique can achieve a 11.13% reduction in average system response time and a 35.21% reduction in translation block erase counts compared with the previous work.

A Fast and Scalable Multi-dimensional Multiple-choice Knapsack Heuristic

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredicatability is an important security feature of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In existing literature on PUFs, Hamming Distance test, denoted by HDT(t), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC(t). The objective of these test schemes is to estimate the output transition probability when there are t or less than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test which is denoted as HDT(e,t). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t. As a contribution, we provide a comprehensive discussion and analytic interpretation of the HDT(t), PC(t) and HDT(e,t) test schemes for Arbiter PUF (APUF), XOR PUF and Lightweight Secure PUF (LSPUF). Our analysis establishes that the HDT(e,t) test is more general in comparison with HDT(t) and PC(t) tests. In addition, we demonstrate scenarios where the adversary can exploit the information obtained from the analysis of HDT(e,t) properties of APUF, XOR PUF and LSPUF to develop statistical attacks on them, if the ideal value of HDT(e,t)=0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and FPGA implemented APUF, XOR PUF and LSPUF designs.

Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices

Commercial off-the-shelf (COTS) reconfigurable devices have been recognized as one of the most suitable processing devices to be applied in nano-satellites, since they can satisfy and combine their most important requirements, namely processing performance, reconfigurability and low cost. However, COTS reconfigurable devices, in particular Static-RAM Field Programmable Gate Arrays (FPGAs), can be affected by cosmic radiation, compromising the overall nano-satellite reliability. Scrubbing has been proposed as a mechanism to repair faults in configuration memory. However, the current scrubbing mechanisms are predominantly static, unable to adapt to heterogeneous applications and their run-time variations. In this paper, a dynamically adaptive scrubbing mechanism is proposed. Through a window-based scrubbing scheduling, this mechanism adapts the scrubbing process to heterogeneous applications (composed by periodic/sporadic and streaming/DSP tasks), as well as their reconfigurations and modifications at runtime. Conducted simulation experiments show the feasibility and the efficiency of the proposed solution in terms of system reliability and memory overhead.

Worst-case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-time Tasks

In this paper, we propose a novel technique that estimates a tight upper bound of worst case response time (WCRT) of a synchronous dataflow (SDF) graph when the SDF graph shares processors with other real time tasks. When an SDF graph is executed at run-time under a self-timed or static assignment scheduling policy on a multi-processor system, static scheduling of the SDF graph does not guarantee the satisfaction of the latency constraint since the timing anomaly behavior may happen. To estimate the WCRT of an SDF graph with a given mapping and scheduling result, we first construct a task instance dependency graph (TIDG) that depicts the dependency between node executions in a static schedule. The proposed technique combines two techniques in a novel way: schedule time bound analysis (STBA) and response time analysis (RTA). The former is used to consider the interference between task instances in the same SDF graph, and the latter is used to consider the interference from other real-time tasks. Based on the proposed WCRT analysis technique, in addition, we propose a genetic algorithm (GA) based framework to solve a design space exploration problem that aims to accommodate the maximum number of real time tasks in a given hardware platform. Through extensive experiments with synthetic examples and benchmarks, we verify the superior performance of the proposed technique compared to other existent techniques.

Multiprocessor Scheduling of a Multi-mode Dataflow Graph Considering Mode Transition Delay

Synchronous Data Flow (SDF) model is widely used for specifying signal processing or streaming applications. Since modern embedded applications become more complex with dynamic behavior changes at run-time, several extensions of the SDF model have been proposed to specify the dynamic behavior changes while preserving static analyzability of the SDF model. They assume that an application has a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. They are classified as multi-mode dataflow models in this paper. While there exist several scheduling techniques for multi-mode dataflow models, no one allows task migration between modes. By observing that the resource requirement can be additionally reduced if task migration is allowed, we propose a multiprocessor scheduling technique of a multi-mode dataflow graph considering task migration between modes. Based on a genetic algorithm, the proposed technique schedules all SDF graphs in all modes simultaneously to minimize the resource requirement. To satisfy the throughput constraint, the proposed technique calculates the actual throughput requirement of each mode and the output buffer size for tolerating throughput jitter. We compare the proposed technique with a method which analyzes SDF graphs in each execution mode separately and a method that does not allow task migration for synthetic examples and three real applications: H.264 decoder, vocoder, and LTE receiver algorithms.

SSAGA: SMs Synthesized for Asymmetric GPGPU Applications

Emergence of GPGPU applications, bolstered by flexible GPU programming platforms, has created a tremendous challenge in maintaining a high energy efficiency in modern GPUs. In this paper, we demonstrate that, customizing a Streaming Multiprocessor (SM) of a GPU, at a lower frequency, is significantly more energy efficient, compared to employing DVFS on an SM, designed for a high frequency operation. Using a system level CAD technique, we propose SSAGAStreaming Multiprocessors Sculpted for Asymmetric GPGPU Applications, an energy efficient GPU design paradigm. SSAGA creates architecturally identical SM cores, customized for different voltage-frequency domains. Our rigorous cross-layer methodology demonstrates an average of 20% improvement in energy efficiency, over a spatially multitasking GPU, across a range of GPGPU applications.

Layer Assignment of Escape buses with Consecutive Constraints in PCB Designs

It is known that it is important for cost and reliability consideration to minimize the number of the used layers and assign the escape buses onto the available layers in a PCB design. In this paper, given a set of n escape buses between two adjacent components and a set of m consecutive constraints on the escape buses, the problem of assigning the given escape buses between two adjacent components onto the available layers is formulated in bus-oriented escape routing. Furthermore, an efficient approach is proposed to minimize the number of the used layers for the given escape buses with the consecutive constraints and assign the escape buses onto the available layers. Compared with Yans approach [J. T. Yan et al. 2012] for the layer assignment of the linear escape buses with no consecutive constraint and Mas approach [Q. Ma, F. Y. Young et al. 2011] for the layer assignment of the circular escape buses with consecutive constraints, the experimental results show that our proposed approach obtains betterl results on the number of the used layers and reduces 43.6% and 90.5% of CPU time for the tested examples on the average, respectively.

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce scan-based tests with one or more functional capture cycles between a scan-in and a scan-out operation. The approach to test generation referred to as transparent-scan has several advantages in this context. (1) It allows functional capture cycles and scan shift cycles to be interleaved arbitrarily. This increases the flexibility to assign to the scan cells values that are needed for diagnosis. (2) Test generation under transparent-scan considers a circuit model where the scan logic is included explicitly. Consequently, the test generation procedure takes into consideration the full effect of a scan chain fault. It thus produces accurate tests. (3) For the same reason it can also target faults inside the scan logic. (4) Transparent-scan results in compact test sequences. Compaction is important because of the large volumes of fail data that scan chain faults create. The cost of transparent-scan is that it requires simulation procedures for sequential circuits, and that arbitrary sequences would be applicable to the scan select input. Motivated by the advantages of transparent-scan, and the importance of diagnosing scan chain faults, this paper describes a procedure for generating transparent-scan sequences for diagnosis of scan chain faults. The procedure is also applied to produce transparent-scan sequences for diagnosis of faults inside the scan logic.

HoPE: Hot-cacheline Prediction for Dynamic Early Decompression in Compressed LLCs

Data compression plays a pivotal role in improving system performance and reducing energy consumption, because it increases the logical effective capacity of a compressed memory system without physically increasing the memory size. However, data compression techniques incur some cost, such as non-negligible compression and decompression overhead. This overhead becomes more severe if compression is used in the cache. In this paper, we aim to lower the read-hit decompression penalty, which significantly increases the cache memory access latency. We demonstrate that the speculative decompression of frequently used cachelines can significantly reduce the read-hit decompression penalty. We hereby propose a Hot-cacheline Prediction and Early decompression (HoPE) mechanism to determine when a compressed cacheline should be decompressed, in order to minimize the total execution time of the system. Additionally, we show that cachelines of similar compressibility often have a high correlation in their hit rates, as data with similar structures is often used in similar ways. Building on this insight, we also propose a compressed cacheline Hit-history-Based Insertion (HBI) policy to take advantage of this correlation, by predicting how often a cacheline will be hit, based on its compressibility. To evaluate the effectiveness of the proposed HoPE mechanism, we run extensive simulations on memory traces obtained from multi-threaded benchmarks running on a full-system simulation framework. We observe significant performance improvements over compressed cache schemes employing the conventional Least-Recently Used (LRU) replacement policy, the Dynamic Re-Reference Interval Prediction (DRRIP) scheme, and the ECM compressed cache management mechanism. Specifically, HoPE exhibits system performance improvements of approximately 11%, on average, over LRU, 8% over DRRIP, and 7% over ECM, by reducing the read-hit decompression penalty by around 65%, over a wide range of applications.

Topological Approach to Automatic Symbolic Macromodel Generation for Analog ICs

In the field of analog integrated circuit design, small-signal macromodels play indispensable roles. However, the subject of automatically generating symbolic low-order macromodels in human readable circuit form has not been well studied. Traditionally, work has been published on reducing full-scale symbolic transfer functions to simpler forms, but without the guarantee of interpretability. In this work a topological reduction method is introduced which is able to automatically generate interpretable macromodel circuits in symbolic form; that is, the circuit elements in the compact model maintain analytical relations of the parameters of the original full circuit. This type of symbolic macromodel has several benefits that other traditional modeling methods do not offer: firstly, reusability, namely, designer need not repeatedly generate macromodels for the same analog integrated circuit when it is either resized or rebiased; secondly, interpretability, namely, designer may identify directly circuit parameters in the original integrated circuit that are closely related to the dominant frequency characteristics, such as dc gain, gain/phase margins, and dominant poles/zeros, etc. The effectiveness and computational efficiency of the proposed method have been validated by several operational amplifier (opamp) circuit examples.

Computation of Seeds for LFSR-Based n-Detection Test Generation

This paper describes a new procedure that generates seeds for LFSR-based test generation when the goal is to produce an n-detection test set. The procedure does not use test cubes in order to avoid the situation where a seed does not exist for a given test cube with a given LFSR. Instead, the procedure starts from a set of seeds that produces a one-detection test set. It modifies seeds to obtain new seeds such that the tests they produce increase the numbers of detections of target faults. The modification procedure also increases the number of faults that each additional seed detects. Experimental results are presented to demonstrate the effectiveness of the procedure.

Symbolic Analyses of Dataflow Graphs

The synchronous dataflow model of computation is widely used to design embedded stream-processing applications under strict quality-of-service requirements (e.g., buffering size, throughput, input-output latency). The required analyses can either be performed at compile time (for design space exploration) or at run-time (for resource management and reconfigurable systems). However, these analyses have an exponential time complexity, which may cause a huge run-time overhead or make design space exploration unacceptably slow. In this paper, we argue that symbolic analyses are more appropriate since they express the system performance as a function of parameters (i.e., input and output rates, execution times). Such functions can be quickly evaluated for each different configuration or checked w.r.t. different quality-of-service requirements. We provide symbolic analyses for computing the maximal throughput of acyclic synchronous dataflow graphs, the minimum required buffers for which as soon as possible scheduling achieves this throughput,and finally the corresponding input-output latency of the graph. The paper first investigates these problems for a simple graph made of a single parametric edge. The results are then extended to general acyclic graphs using linear approximation techniques. We assess the proposed analyses experimentally on both synthetic and real benchmarks.

ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems

Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and QoS guarantees on multiprocessors, form an attractive alternative in real-time embedded systems that concurrently run a mix of independent applications with varying timeliness constraints. This paper presents "ERfair Scheduler with Suspension on Multiprocessors" (ESSM), an efficient, optimal proportional fair scheduler that attempts to reduce system wide energy consumption by locally maximizing the processor suspension intervals while not sacrificing the ERfairness timing constraints of the system. The proposed technique takes advantage of higher execution rates of tasks in underloaded ERfair systems and uses a procrastination scheme to search for time points within the schedule where suspension intervals are locally maximal. Evaluation results reveal that ESSM achieves good sleep efficiency and provides upto 50% higher effective total sleep durations as compared to the Basic-ERfair scheduler on systems consisting of 2 to 20 processors.

Non-enumerative Generation of Path Delay Distributions and its Application to Critical Path Selection

A Monte Carlo based approach is proposed capable of identifying in a path-implicit and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

System Level Design Approaches to Security in Automotive Networks

With the increasing amount of interconnections between vehicles, the attack surface of internal vehicle networks is rising steeply. Although these networks are shielded against external attacks, they often do not have any internal security to protect against malicious components or adversaries who can breach the network perimeter. To secure the in-vehicle network, all communicating components must be authenticated, and only authorized components should be allowed to send and receive messages. This is achieved through an authentication framework. Cryptography is widely used to authenticate communicating parties and provide secure communication channels (e.g. Internet communication). However, real-time performance requirements of in-vehicle networks restrict the types of cryptographic algorithms and protocols that may be used. In particular, asymmetric cryptography is computationally infeasible during vehicle operation. In this work, we address the challenges of designing authentication protocols for automotive systems. We present Lightweight Authentication for Secure Automotive Networks (LASAN), a full life-cycle authentication approach. We describe the LASAN protocols and show how they protect the internal vehicle network while complying with the real-time constraints and low computational resources of this domain. Unlike previous work, we also explain how LASAN can be integrated into all aspects of the automotive product life cycle, including manufacturing and maintenance. We evaluate LASAN in two ways: Firstly, we analyze the security of the protocols using established protocol verication based on formal methods. Secondly, we evaluate the timing requirements of LASAN and compare these to other frameworks using a new discrete event simulator for in-vehicle networks.

Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control

To alleviate high energy dissipation of unnecessary snooping accesses, snoop filter designs have been proposed to reduce snoop lookups. These filters have the problem of decreasing filtering efficiency, and thus usually rely on partial or whole filter reset by detecting block evictions. Unfortunately, the reset conditions occur infrequently or unevenly (named as passive filter deletion). This work proposes the concept of revitalized snoop filter (RSF) design, which can actively renew the destination filter by employing a generation wrapping around scheme for various reference behaviors. We further utilize a sampling mechanism for RSF to timely trigger precise filter revitalizations, so that unnecessary RSF flushing can be minimized. The proposed RSF can be integrated to various inclusive snoop filters and needs only minor change to their designs. We evaluate our proposed design and demonstrate that RSF eliminates 58.6% of snoop energy compared to JETTY on average while inducing only 6.5% of revitalization energy overhead. In addition, RSF eliminates 45.5% of snoop energy compared to stream registers on average and only induces 2.5% of revitalization energy overhead. Overall, these RSFs reduce the total L2 cache energy consumption by 52.1% (58.6%-6.5%) as compared to JETTY and by 43% (45.5%-2.5%) as compared to stream registers. Furthermore, RSF improves the overall performance by 1% to 1.4% on average compared to JETTY and Stream Registers for various benchmark suites.

A List of Fundamental Challenges Towards Making IoT a Reachable Reality: A Model-centric Investigation

The constantly advancing integration capability is paving the way to the construction of extremely large scale continuum of internet where entities, or things, from vastly varied domains are uniquely address- able and interacting seamlessly to form a giant networked system of systems, known as Internet-of-things (IoT). In contrast to such visionary networked system paradigm, prior research efforts on IoT are still very fragmented and confined to disjoint explorations in different application, architectural, security, services, protocol and economical domains, thus preventing the design exploration and optimization from a unified and global perspective. In this context, this survey article first proposes a mathematical modeling frame- work that is rich in expressivity to capture the IoT characteristics from a global perspective. Then a list of fundamental challenges in i) sensing , ii) decentralized computation, iii) energy-efficiency and iv) hardware security is identified and formulated based on the proposed modeling framework. The solutions are discussed to shed lights on future IoT system paradigm development.

Low-Power Clock Tree Synthesis for 3D-ICs

We propose efficient algorithms to construct low-power clock tree for through-silicon-via (TSV) based 3D-ICs. We use shutdown gates to save clock tree's dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering. (2) Clock tree embedding with simultaneous shutdown gates insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that: (1) The K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity. (2) The SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis technique, our K-means clustering based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

PeaPaw: Performance and Energy Aware Partitioning of Workload on Heterogeneous Platforms

Performance and energy are two major concerns for application development on heterogeneous platforms. It is challenging for application developers to fully exploit the performance/energy potential of heterogeneous platforms. One reason is the lack of reliable prediction of the system's performance/energy before application implementation. Another reason is that a heterogeneous platform presents a large design space for workload partitioning between different processors. To reduce such development cost, this paper proposes a framework, PeaPaw, to assist application developers to identify a workload partition (WP) that has high potential leading to high performance or energy efficiency before actual implementation. The PeaPaw framework includes both analytical performance/energy models and two sets of workload partitioning guidelines. Based on the design goal, application developers can obtain a workload partitioning guideline from PeaPaw for a given platform and then follow it to design one or multiple WPs for a given workload. Then PeaPaw can be used to estimate the performance or energy of the designed WPs, and the WP with the best estimated performance or energy will be selected for further implementation. To demonstrate the effectiveness of PeaPaw, we have conducted three case studies. Results from these case studies show that PeaPaw can faithfully estimate the performance/energy relationships of WPs and provide effective workload partitioning guidelines.

Application-Specific Residential Microgrid Design Methodology

In power system industry, the traditional, non-interactive, and manually-controlled power grid has been transformed to cyber-dominated smart grid. This cyber-physical integration has provided the smart grid with communication, monitoring, computation, and controlling capabilities to improve its reliability, energy efficiency, and flexibility. A microgrid as a localized and semi-autonomous group of smart energy systems, utilizes the above-mentioned capabilities to drive modern technologies such as electric vehicle charging, home energy management, smart appliances, etc. Designing, upgrading, testing, and verifying these microgrids can get too complicated to handle manually. The complexity is due to the wide range of solutions and components that are intended to address the microgrid problems. This paper presents a novel Model-Based Design (MBD) methodology to model, co-simulate, design, and optimize microgrid and its multi-level controllers. It helps us to design, optimize, and validate a microgrid for a specific application. The application rules, requirements, and design-time constraints are met in the designed/optimized microgrid while the implementation cost is minimized. Based on our novel methodology, a design automation, co-simulation, and analysis tool, called GridMAT, is implemented. Our experiments have illustrated that implementing a hierarchical controller reduces the average power consumption by 8% and shifts the peak load for cost saving. Moreover, using our MBD methodology with smart controllers, the total implementation cost decreases by 14%, when upgrading a microgrid, compared to the conventional methodology and 5%, compared to the case where smart controllers are not considered.

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems

The design of the communication infrastructure of electronic systems has a significant impact on their cost, performance and time-to-market. However, the design and Design Space Exploration of communication protocols and patterns are typically subject to the design of processing operations (computations) and to their mapping onto execution resources. This strategy prevents to study and evaluate the impact of interdependencies between computations and communications (e.g., impact of application traffic patterns onto the communication interconnect). To solve this issue we introduce a novel design approach - the ¨-chart - where we design communication patterns and protocols independently of a systems application and platform, via dedicated models. At mapping step, the functionality of both application and communication models is associated to the platforms resources thus allowing for the joint Design Space Exploration of computations and communications. We present the overall design approach, the communication models and their implementation in TTool/DIPLODOCUS, a UML/SysML framework for the modeling, simulation, formal verification and automatic code generation of data-flow embedded systems. The effectiveness of our approach in terms of better design quality and Design Space Exploration is demonstrated with the design of the physical layer of a ZigBee (IEEE 802.15.4) transmitter onto a multi-processor architecture.

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Recently, phase change memory (PCM) is emerging as a strong replacement for DRAM owing to its many advantages such as non-volatility, high scalability, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by reducing bit flips. Although they have significantly contributed to bit flip reduction, they still have the drawback that the lower bits are flipped more often than the higher bits. The reason is that these methods do not consider the fact that, in general, the lower bits are updated much more frequently than the higher bits. In this paper, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. Specifically, CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method, while consuming a few extra resources for metadata. We have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

A Matlab Vectorizing Compiler Targeting Application Specific Instruction Set Processors

This paper discusses a MATLAB to C vectorizing compiler that exploits custom instructions e.g. for SIMD processing and instructions for complex arithmetic present in Application Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code and the generated code can be used as input to any C/C++ compiler. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor independent architecture description approach thus allowing the support of any processor. The proposed compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the proposed compiler achieves a speed up between 2x-10x and 2x-30x compared to the code generated by Mathworks MATLAB-to-C compiler. Experimental results also prove that the proposed compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speed up compared to cases where no SIMD processing is used. Thus the proposed compiler can be employed to reduce the development time / effort / cost and time to market through raising the abstraction of application design in an embedded systems / system-on-chip development context.

CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability and Authentication in IoT Supply Chain

The Internet of Things (IoT) is transforming the way we live and work by increasing the connectedness of people and things on a scale that was once unimaginable. However, the vulnerabilities in IoT supply chain have raised serious concerns about the security and trustworthiness of IoT devices and components on them. Testing for device provenance, detection of counterfeit integrated circuits (ICs) and systems, and traceability of IoT devices are challenging issues to address. In this paper, we develop a novel RFID-based system suitable for Counterfeit Detection, Traceability and Authentication in IoT supply chain called CDTA. CDTA is composed of different types of on-chip sensors and in-system structures that collect necessary information to detect multiple counterfeit IC types (recycled, cloned, etc.), track and trace IoT devices, and verify the overall system authenticity. Central to CDTA is an RFID tag employed as storage and a channel to read the information from different types of chips on the printed circuit board (PCB) in both power-on and power-off scenarios. A novel board ID generator is implemented by combining outputs of physical unclonable functions (PUFs) embedded in RFID tag and different chips on the PCB. A light-weight RFID protocol is proposed to enable mutual authentication between RFID readers and tags. We also implement a secure inter-chip communication on the PCB. Simulations and experimental results using Spartan 3E FPGAs demonstrate the effectiveness of this system. The efficiency of the radio frequency (RF) communication has also been verified via a PCB prototype with a printed slot antenna.

Scale&Cap: Scaling-Aware Resource Management for Consolidated Multi-threaded Applications

As the number of cores per server node increases, designing multi-threaded applications has become essential to efficiently utilize the available hardware parallelism. Many application domains have started to adopt multi-threaded programming; thus, the efficiently managing the execution of multi-threaded applications is also growing. Efficient execution of multi-threaded workloads on cloud environments, where applications are often consolidated by means of virtualization, relies on understanding the multi-threaded specific characteristics of the applications. Furthermore, energy cost and power delivery limitations require data center server nodes to work under power caps, which bring additional challenges to runtime management of consolidated multi-threaded applications. This paper proposes a dynamic resource allocation technique for consolidated multi-threaded applications for power-constrained environments. Our technique takes into account application characteristics specific to multi-threaded applications, such as power and performance scaling, to make resource distribution decisions at runtime to improve the overall performance, while accurately tracking dynamic power caps. We implement and evaluate our technique on state-of-the-art servers and show that the proposed technique improves the application performance by up to 24% under power cap compared to default resource manager.

Optimized Implementation of Multi-Rate Mixed-Criticality Synchronous Reactive Models

Model-based design using Synchronous Reactive (SR) models enables early verification of functionality, and helps to cope with the increasing complexity of modern embedded systems. Mixed-Criticality Scheduling (MCS) is an effective approach to addressing diverse certification requirements of safety-critical systems that integrate multiple subsystems with different levels of criticality. This paper considers fixed-priority scheduling of mixed-criticality SR models, and explores two scheduling techniques: one is based on Adaptive Mixed-Criticality scheduling, the other based on Elastic Mixed-Criticality Scheduling. We present a branchand- bound procedure and a heuristic algorithm to minimize the total system cost of functional delays in the implementation.

Temperature Effect Inversion Aware Dynamic Thermal Management for FinFET Circuits

Due to the superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the gate delay vs. temperature characteristics of FinFET circuits may be fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Fur- thermore, with the optimal buffer insertion, we have observed that interconnect delay of the FinFET circuits may follow the same trend for the temperature change. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET circuits without any appreciable performance penalty. Experi- mental results demonstrate that significant energy saving (as high as 36%, with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

A Survey of Parametric Dataflow Models of Computation

Dataflow models of computation (MoCs) are widely used to design embedded signal processing and streaming systems. Dozens of dataflow MoCs have been proposed in the few last decades. More recently, several parametric dataflow MoCs have been presented as an interesting trade-off between analyzability and expressiveness. The dynamism is controlled and takes the form of parameters (e.g., parametric rates) and run-time parameter configuration. This paper first strives to formalize or clarify criteria used to compare dataflow MoCs. It then provides a comprehensive description of the existing parametric dataflow MoCs (constructs, constraints, properties, static analyses) which may help designers of streaming applications to choose the most suitable model for their needs.

Critical-Path-Aware High-Level Synthesis with Distributed Controller for Fast Timing Closure

Secure and Flexible Trace-Based Debugging of Systems-on-Chip

This work tackles the conflict between securing assets in a system-on-chip (SoC) and observing the internal state of the SoC during trace-based debugging. On one hand, security objectives require that assets remain confidential throughout the SoC life-cycle. On the other hand, the SoC trace-based debug architecture exposes values of internal signals that can leak the assets to third-parties. We propose a secure trace-based debug infrastructure to resolve this conflict. The infrastructure tags each asset to identify its owner (who it can be exposed to during debug), and enhances the debug architecture with security features to enforce the confidentiality of assets. We implement a prototype of the enhanced debug architecture on FPGA to validate its functional correctness. ASIC evaluations show that our approach incurs area and power costs of 7% on a processor used in commodity SoCs.

Scalable SMT-based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis

In this paper, we present a novel methodology based on SMT-solvers to verify equality of a high level described specification and a pipelined RTL implementation produced by a high level synthesis tool. The complex transformations existing in the high level synthesis process, such as nested loop pipelining, cause the conventional methods of equivalence checking to be inefficient. The proposed equivalence checking method attacks simultaneously to the two problems in this context: 1) state space explosion and 2) complex high level synthesis transformations. To show the scalability and efficiency of the proposed method, the verification results of large industrial designs are compared with those of the SAT-based method, including three different state-of-the-art SAT-solvers, the SMT-based procedure, the modular Horner expansion diagram (M-HED) based method, and the M-HED partitioning approach. The results show interesting improvements in terms of time and memory usage in comparison with other methods. Furthermore, using the proposed equivalence checking approach, fault tolerance issues can be formally analyzed in the presence of some faults in the designs.

Reducing the Complexity of Dataflow Graphs using Slack-based Merging

There exist many dataflow applications with timing constraints that require real-time guarantees on safe execution without violating their deadlines. Extraction of timing parameters (offsets, deadlines, periods) from these applications enables the use of real-time scheduling and analysis techniques, and provides guarantees on satisfying timing constraints. However, existing extraction techniques require the transformation of the dataflow application from highly expressive dataflow computational models, e.g., Synchronous Dataflow (SDF) and Cyclo-Static Dataflow (CSDF) to Homogeneous Synchronous Dataflow (HSDF). This transformation can lead to an exponential increase in the size of the application graph that significantly increases the run-time of the analysis. In this article, we address this problem by proposing an algorithm called slack-based merging that generates a reduced-size HSDF graph from a given SDF graph with timing constraints. This algorithm is based on a novel concept of merging called safe merge, which is a merge operation that we formally prove that it cannot cause a live HSDF graph to deadlock. The results show that the reduced graph: 1) respects the throughput and latency constraints of the original application graph and 2) typically speeds up the process of extracting timing parameters and finding a feasible real-time schedule for real-time dataflow applications. They also show that when the throughput constraint is relaxed with respect to the maximal throughput of the graph, the merging algorithm is able to achieve a larger reduction in graph size, which in turn results in a larger speed-up of the real-time scheduling algorithms.


Publication Years 1996-2016
Publication Count 877
Citation Count 4177
Available for Download 877
Downloads (6 weeks) 2229
Downloads (12 Months) 21292
Downloads (cumulative) 358755
Average downloads per article 409
Average citations per article 5
First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Distinguished Member (2008)
ACM Senior Member (2006)
Naehyuck Chang ACM Distinguished Member (2012)
ACM Senior Member (2007)
Danny Z Chen ACM Distinguished Member (2014)
ACM Senior Member (2011)
Nikil D. Dutt ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
Soheil Ghiasi ACM Senior Member (2015)
Matthew Guthaus ACM Senior Member (2013)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
John Lee ACM Senior Member (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Ian Parberry ACM Distinguished Member (2015)
Massoud Pedram ACM Distinguished Member (2008)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
Robert Schreiber ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 17
Nikil Dutt 15
Irith Pomeranz 14
Krishnendu Chakrabarty 13
Jason Cong 12
Sheldon Tan 10
TingTing Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
Lei He 8
Yaowen Chang 8
Yunheung Paek 7
Evangeline Young 7
Frank Vahid 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Massoud Pedram 6
Radu Marculescu 6
Sudhakar Reddy 6
Bhargab Bhattacharya 6
Spyros Tragoudas 6
Chengkok Koh 6
Martin Wong 6
Alexandru Nicolau 6
John Hayes 6
Igor Markov 6
Ryan Kastner 6
Taewhan Kim 6
Ali Dasdan 5
Sule Ozev 5
Sharad Malik 5
David Pan 5
Kiyoung Choi 5
Kaushik Roy 5
Mahmut Kandemir 5
Umit Ogras 5
Jenqkuen Lee 5
Preeti Panda 5
Rajeev Kumar 5
Aviral Shrivastava 5
Giovanni De Micheli 5
Andrew Kahng 5
Tony Givargis 5
Roman Lysecky 5
Nagarajan Ranganathan 5
Chungkuan Cheng 5
Kwangting Cheng 4
Rajesh Gupta 4
Zijiang Yang 4
Sunil Khatri 4
El Aboulhamid 4
Jingyang Jou 4
Aarti Gupta 4
Xiaobosharon Hu 4
Pinghung Yuh 4
Shihhsu Huang 4
Peter Petrov 4
Peng Li 4
Iris Jiang 4
Ramesh Karri 4
Yuanhao Chang 4
Alex Jones 4
Hungming Chen 4
Sunyuan Hsieh 4
Hans Wunderlich 4
Chang Liu 4
Jintai Yan 4
Allen Wu 4
Naehyuck Chang 4
Miodrag Potkonjak 4
Jongeun Lee 4
Dinesh Mehta 4
Paul Gratz 4
Franco Fummi 4
Paulo Flores 4
Hai Zhou 4
Dirk Stroobandt 4
Azadeh Davoodi 4
Greg Stitt 3
Li Wang 3
Chakkuen Wong 3
Waikei Mak 3
Krishnendu Chakrabarty 3
Seda Memik 3
Henk Corporaal 3
Dimitrios Kagaris 3
Praveen Raghavan 3
Martin Lukasiewycz 3
Karel Bruneel 3
Soonhoi Ha 3
Valeria Bertacco 3
Viktor Prasanna 3
Yuan Xie 3
Diana Marculescu 3
Ozgur Sinanoglu 3
Jürgen Teich 3
Ronald Blanton 3
Paolo Prinetto 3
Sebastian Steinhorst 3
Sreejit Chakravarty 3
Paoann Hsiung 3
Wen Jone 3
Guangming Wu 3
Axel Jantsch 3
Sisira Panda 3
Zoran Salcic 3
Dipankar Das 3
Prabhat Mishra 3
Masanori Kurimoto 3
Guy Gogniat 3
Yuchin Hsu 3
Xiaoyu Song 3
Yunsi Fei 3
Anna Bernasconi 3
Janet Roveda 3
Ozcan Ozturk 3
Arnout Vandecappelle 3
Chenjie Yu 3
Peter Cheung 3
Costas Goutis 3
Youngsoo Shin 3
Shiyu Huang 3
Karem Sakallah 3
Chungwen Huang 3
Valentina Ciriani 3
Juan Maestro 3
Massimo Poncino 3
Fadi Kurdahi 3
Partha Roop 3
Mehdi Tahoori 3
Tsungyi Ho 3
Alberto Sangiovanni-Vincentelli 3
Zonghua Gu 3
Gianpiero Cabodi 3
Seongnam Kwon 3
Soheil Ghiasi 3
Kurt Keutzer 3
Sarma Vrudhula 3
Thambipillai Srikanthan 3
Pai Chou 3
Martin Palkovič 3
Yowtyng Nieh 3
Pedro Reviriego 3
Daniel Gajski 3
Xiangrong Zhou 3
Madhu Mutyam 3
David Atienza 3
Majid Sarrafzadeh 3
Janak Patel 3
Per Kjeldsberg 3
José Monteiro 3
Chialin Yang 3
Domenic Forte 3
Chiuwing Sham 3
Edwin Sha 3
Baris Taskin 3
Yinhe Han 3
Dong Xiang 3
Nicholas Zamora 3
Saojie Chen 3
Elizabeth Rudnick 3
Enrico Macii 3
Ankur Srivastava 3
Hai Wang 3
Shuvra Bhattacharyya 3
Priyank Kalla 3
Yiping You 3
Teiwei Kuo 3
Twan Basten 3
Hao Yu 3
George Constantinides 3
Shihchieh Chang 3
Xianlong Hong 3
Srinivas Katkoori 2
Andreas Dandalis 2
Mohammad Arjomand 2
Guolong Chen 2
Yi Wang 2
Janming Ho 2
Sudhakar Yalamanchili 2
Qinru Qiu 2
Bo Zhao 2
Deepak Mathaikutty 2
Robert Walker 2
Maria Michael 2
Tsungyi Ho 2
Picheng Hsiu 2
Natarajan Viswanathan 2
Román Hermida 2
Christophe Wolinski 2
Yongjoo Kim 2
Alper Sen 2
Wim Heirman 2
Dimitrios Soudris 2
Zebo Peng 2
Jagannathan Ramanujam 2
Erik Brockmeyer 2
Inki Hong 2
Sanghamitra Roy 2
Duncan Walker 2
Farinaz Koushanfar 2
Naiwen Chang 2
Masahiro Fujita 2
Sivaram Gopalakrishnan 2
Gary Dispoto 2
Chiachun Tsai 2
Chrystian Guth 2
Haibao Chen 2
Yuliang Wu 2
Jun Yang 2
Jhihrong Gao 2
Seokhyeong Kang 2
Sarmishtha Ghoshal 2
Swapna Dontharaju 2
Kees Goossens 2
Chao Wang 2
Chinhsien Wu 2
Meikang Qiu 2
Masato Edahiro 2
Angeliki Kritikakou 2
Joann Paul 2
Konstantin Moiseev 2
Jun Yang 2
Jun Zeng 2
Luigi Carro 2
Chingren Lee 2
Hafizur Rahaman 2
Jin Sun 2
Swaminathan Narayanaswamy 2
Leyla Nazhandali 2
Akash Kumar 2
Timothy Sherwood 2
Bijan Alizadeh 2
Hai Wang 2
Shihhao Hung 2
Wayne Wolf 2
Steven Wilton 2
Graziano Pravadelli 2
John Gough 2
Avinash Malik 2
Jörg Henkel 2
Swarup Bhunia 2
Susmita Sur-Kolay 2
Guangyu Chen 2
Paul Thadikaran 2
Marc Boulé 2
Chienchih Huang 2
Chinlong Wey 2
Jwu Chen 2
Younlong Lin 2
C Shi 2
Yiyu Shi 2
Laungterng Wang 2
Arnab Roy 2
Xing Huang 2
Peter Milder 2
Hui Liu 2
Guihai Yan 2
Ricardo Reis 2
Siddharth Garg 2
Nicola Bombieri 2
Jiping Liu 2
Radu Marculescu 2
Puneet Gupta 2
Jinyong Lee 2
Yongje Lee 2
Jos Huisken 2
Mark Tehranipoor 2
James Cain 2
Leonid Mats 2
Marco Bekooij 2
Franjo Ivančić 2
Maurizio Rebaudengo 2
Kiwook Kim 2
Russell Tessier 2
Kyumyung Choi 2
Vigyan Singhal 2
Srinivas Devadas 2
Sujit Dey 2
Ismail Kadayif 2
Levent Aksoy 2
Smita Bakshi 2
Siddhartha Mukhopadhyay 2
Rudy Lauwereins 2
Jingyang Jou 2
Francesco Poletti 2
Miguel Miranda 2
Ingoo Heo 2
Sudip Roy 2
Marlin Mickle 2
Hiroaki Inoue 2
Kanupriya Gulati 2
Luís Silveira 2
Ali Afzali-kusha 2
Vivek Sarin 2
Yiyu Liu 2
Deming Chen 2
José Mendías 2
Ronald Graham 2
M Balakrishnan 2
Stan Liao 2
Mike Lee 2
Ansuman Banerjee 2
Sreeranga Rajan 2
Avinoam Kolodny 2
Mary Irwin 2
Michael Kochte 2
Erik Marinissen 2
Genggeng Liu 2
Wenzhong Guo 2
Samarjit Chakraborty 2
Meeta Srivastav 2
Bart Mesman 2
Muhammet Ozdal 2
Bei Yu 2
Yiyu Shi 2
Shenchih Tung 2
Dawei Chang 2
Mario López 2
Kun Yuan 2
Arcot Sowmya 2
Rajdeep Mukhopadhyay 2
Peichen Pan 2
Chung Tsao 2
Javed Absar 2
Murali Jayapala 2
Lei Li 2
Krzysztof Kuchcinski 2
Yvon Savaria 2
Xin Yuan 2
Peiwen Luo 2
Aiqun Cao 2
Roberto Passerone 2
Luciano Lavagno 2
Min Xu 2
Michel Auguin 2
Freek Verbeek 2
Vijaykrishnan Narayanan 2
Michael Hsiao 2
Xuexin Liu 2
Anmol Mathur 2
Sergio Nocco 2
Zhiyu Zeng 2
Koushik Chakraborty 2
Chiajui Hsu 2
José Pino 2
Dongsheng Ma 2
Jochen Jess 2
Peng Li 2
Shmuel Wimer 2
Rafal Baranowski 2
Bin Liu 2
Kaihui Chang 2
Pochun Huang 2
Bocheng Lai 2
José Güntzel 2
Xin Li 2
Sandeep Shukla 2
Eduard Cerny 2
Jun Gu 2
Poyuan Chen 2
Junji Sakai 2
Abhijit Jas 2
Sungmo Kang 2
Junjuan Xu 2
Vasilios Kelefouras 2
Sungjoo Yoo 2
Sunggu Lee 2
Chandra Suresh 2
Melvin Breuer 2
Marco Murciano 2
Xiaoping Hu 2
Manfred Glesner 2
Jim Holt 2
Magdy Abadir 2
Adnan Aziz 2
Saraju Mohanty 2
Tajana Rosing 2
Željko Žilić 2
Chunjason Xue 2
Michael Riepe 2
Stefano Quer 2
Mohammad Tehranipoor 2
Luiz Dos Santos 2
Ranga Vemuri 2
Mehrdad Nourani 2
Kai Zhu 2
ChengHsing Yang 2
Nur Touba 2
Hyesoon Kim 2
Elaheh Bozorgzadeh 2
Hongbing Fan 2
Shantanu Dutt 2
Paul Bogdan 2
Hiren Patel 2
Chiaming Chang 2
Donald Thomas 2
Hsinhung Chen 2
S Ramesh 2
Matteo Reorda 2
Guido Araújo 2
Fei Su 2
Wayne Luk 2
P Chakrabarti 2
Matthew Guthaus 2
Gustavo Wilke 2
Julien Schmaltz 2
Qing Duan 2
Markus Püschel 2
Zili Shao 2
Doosan Cho 2
Vinícius Livramento 2
Chittaranjan Mandal 1
Joan Lopez 1
ChungHwang Chen 1
Michael Boyer 1
Srikanth Venkataraman 1
Horácio Neto 1
JyhMou Tseng 1
Joseph Shinnerl 1
Qingan Li 1
Esteban Tlelo-Cuautle 1
Klaus Eckl 1
Kuenjong Lee 1
Tsungchu Huang 1
Andrew Wolfe 1
Yau Li 1
Huankai Peng 1
HsuanMing Huang 1
Wanting Lo 1
Chiehjui Lee 1
Paolo Camurati 1
K Tsai 1
Chandu Visweswariah 1
Raj Nadakuditi 1
Shashidhar Thakur 1
Adrian Ludwin 1
Tiempo Sas 1
Wenjong Fang 1
Yuhao Zhu 1
Michael Hsiao 1
James Li 1
Vincent Mooney 1
Matthew Gately 1
Scott Little 1
David Bild 1
Gregory Bok 1
Gauthier Lafruit 1
Claudio Sansoè 1
Piet Engelke 1
Sally McKee 1
Keshab Parhi 1
Kevin Lepak 1
Gerda Janssens 1
Wenrui Gong 1
Brian DeRenzi 1
Michael Mefenza 1
Hsiangpang Li 1
Jingwei Lu 1
Said Hamdioui 1
Adwait Gupte 1
Nathan Denny 1
J Chen 1
Stephen Cauley 1
Ying Hu 1
U Rovati 1
William Hung 1
Sumit Gupta 1
Ausif Mahmood 1
Yufu Zhang 1
Seongook Jung 1
Ali Pınar 1
Yongwen Wang 1
Stephen Edwards 1
Jackey Yan 1
Chris Chu 1
Dominik Erb 1
Matthias Sauer 1
Tobias Schubert 1
Minseok Kang 1
Baktash Boghrati 1
Claudio Talarico 1
Ying Qin 1
Shengyu Shen 1
Huadong Dai 1
Qi Zhu 1
Waishing Luk 1
Hai Wang 1
Tim Nieberg 1
José Costa 1
Ying Tan 1
Haotse Chen 1
Dacheng Juan 1
Diana Marculescu 1
Gwan Choi 1
Dip Goswami 1
Ramin Fallahzadeh 1
Fubing Mao 1
Hai Li 1
Hongfei Wang 1
Hosoon Shin 1
Qihang Shi 1
Linzhang Wang 1
Namita Sharma 1
Emmanuelle Encrenaz 1
Jean Desbarbieux 1
Safar Hatami 1
Ganghee Lee 1
Youtao Zhang 1
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Giorgio Natale 1
Qiang Ma 1
Martin Wong 1
Hamid Shojaei 1
Yaolin Chang 1
Yongjoo Kim 1
Sanghyun Park 1
Yahya Osais 1
Markus Seuring 1
Randall Geiger 1
Degang Chen 1
Pinar Korkmaz 1
Yan Lin 1
Raymond Hoare 1
John Lockwood 1
Sabyasachi Das 1
Huaizhi Wu 1
Sudarshan Bahukudumbi 1
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Francesco Zanini 1
Colin Jones 1
Krste Asanović 1
Naifeng Jing 1
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Chaohung Lu 1
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Nan Guan 1
Carlos González 1
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Yici Cai 1
Antonio Garcia-Dopico 1
Fangfang Li 1
Stefanus Mantik 1
Puneet Gupta 1
Hai Lin 1
Mark Yeary 1
Vissarion Ferentinos 1
Dennis Sylvester 1
Erwan Raffin 1
K Yuan 1
D Van Campenhout 1
Trevor Mudge 1
Rick McGeer 1
Chunghsiang Lin 1
Miad Faezipour 1
Byunghyun Lee 1
Ken Kennedy 1
Yuzheng Ding 1
Sharat Prasad 1
David Whalley 1
ChuangYi Chiu 1
Ilia Polian 1
Ingjer Huang 1
Bruno Lavigueur 1
Zhihua Zhou 1
Dennis Huang 1
Chungkuan Cheng 1
Dong Lee 1
Geert Deconinck 1
Hsueh Lu 1
Nobuhiro Tsuda 1
Yi Zou 1
Donatella Sciuto 1
Arijit Ghosh 1
C Krishna 1
Kaijie Wu 1
Wennai Cheng 1
Xuan Guan 1
Guoqiang Chen 1
Yunchih Chang 1
Michael Glaß 1
Zhiying Wang 1
Jieun Lim 1
Nagesh Lakshminarayana 1
Bernd Becker 1
Waseem Ahmed 1
Kamyiu Lam 1
Debashri Roy 1
Debasis Mitra 1
Chiawei Lee 1
Yunfeng Yang 1
Brian Tagiku 1
Bailey Miller 1
El Bourennane 1
Ashish Gupta 1
Hungming Chen 1
Christian Schulte 1
ChunDa Du 1
Alfredo Benso 1
James Huggins 1
Claudio Passerone 1
Nakwoong Eum 1
Annette Bunker 1
Michael Birbas 1
Pierre Paulin 1
Gang Wang 1
Chris Ostler 1
Pengwen Chen 1
Chinchih Chang 1
Sudhanshu Vyas 1
Kai Huang 1
Alois Knoll 1
Chengyen Lin 1
Guangyu Sun 1
Huazhong Yang 1
Rensong Tsay 1
Zhiwei Qin 1
Xiaowei Li 1
Yuning Chang 1
Maciek Kormicki 1
Rajkumar Raval 1
Carl Pixley 1
Yang Xu 1
Libo Huang 1
Hsiangyun Cheng 1
Huahsin Yeh 1
Jinkyu Koo 1
Hu Chen 1
Anupama Subramaniam 1
V Kamakoti 1
Seonwook Kim 1
Hai Zhou 1
Jongwon Lee 1
Rico Backasch 1
Luca Benini 1
Davide Rossi 1
Yungchih Chen 1
Roozbeh Jafari 1
Vinita Vasudevan 1
Yang Xu 1
Jaeyeon Won 1
Xuandong Li 1
Malgorzata Marek-Sadowska 1
Sudheendra Kadri 1
Keesung Han 1
Hyunjik Song 1
Junhee Yoo 1
Jun Lu 1
Songbin Pan 1
Kunlin Tsai 1
Gungyu Pan 1
Arne Meeuw 1
Taeyoung Kim 1
Vikas Vij 1
Jiang Hu 1
Chen Zhao 1
Tong Xu 1
Stefan Holst 1
Michael Imhof 1
Navin Vemuri 1
Rajeev Jayaraman 1
Abusaleh Jabir 1
Andreas Raabe 1
Philipp Hartmann 1
George Viamontes 1
Ningde Xie 1
Tong Zhang 1
Hyungjun Kim 1
Tan Yan 1
Si Li 1
Reiley Jeyapaul 1
Dana Price 1
Xiang Lu 1
Fernanda De Lima 1
Wei Wu 1
Sungkyu Lim 1
Krishna Palem 1
Eugenio Villar 1
Román Hermida 1
Youngpyo Joo 1
Davide Bertozzi 1
Kishore Muchherla 1
Luiz Santos 1
Panagiotis Manolios 1
Brett Brotherton 1
Wilsin Gosti 1
Manuel Prieto 1
Yiwen Shi 1
Shravan Muddasani 1
Srinivas Boppu 1
John Lee 1
Luca Benini 1
Christopher Batten 1
R Iris Bahar 1
Zhigang Mao 1
Zhe Feng 1
Chien Liu 1
Nastaran Baradaran 1
David Bol 1
Paul Franzon 1
Mango Chao 1
Cong Xu 1
Shimeng Yu 1
Stavros Hadjitheophanous 1
Yingchi Li 1
Mohammad Samavatian 1
Anand Raghunathan 1
Ran Wang 1
Andreas Hoffmann 1
Scott Mahlke 1
Feipei Lai 1
Su Gao 1
Alessandro Bogliolo 1
Niall O'Neill 1
Vincenza Carchiolo 1
Doris Ching 1
Roopak Sinha 1
Mohamed Basiri M 1
Noor Sk 1
Shobha Vasudevan 1
Mateo Valero 1
Hsienkai Kuo 1
Amit Chowdhary 1
John Lillis 1
Zainalabedin Navabi 1
João Marques-Silva 1
Furshing Tsai 1
Kijin Han 1
Youngmin Kim 1
Mark Lin 1
Toru Fujimura 1
Jinglei Huang 1
Song Chen 1
Sangmin Kim 1
Chiying Tsui 1
Sebastian Fischmeister 1
Peishan Tu 1
Chao Wang 1
Robert CzerwińSki 1
Hao Wu 1
Zhenghong Zhang 1
Hiroyuki Kondo 1
Hai Li 1
Jiang Hu 1
Marc Geilen 1
Marie Flottes 1
Alex Jones 1
Aiman El-Maleh 1
Egor Sogomonyan 1
Wangqi Qiu 1
Zhuo Li 1
Pokuan Huang 1
Suchismita Roy 1
Mingyung Ko 1
Suren Ramasubbu 1
TzuTeng Lin 1
Michalis Galanis 1
Fernando Herrera 1
Paul Mesa 1
Sungchan Kim 1
Iyad Al Khatib 1
Rustam Nabiev 1
Daniel Casarotto 1
Peter Hawrylak 1
Yajun Ha 1
Ted Huffmire 1
Jonathan Valamehr 1
I Tseng 1
Amit Singh 1
Kiamal Pekmestzi 1
Vahid Lari 1
Ayse Coskun 1
Somsubhra Mondal 1
Qingxu Deng 1
Jean Legat 1
Gaurav Dhiman 1
Seyed Miremadi 1
Ali Mirtar 1
Karel Heyse 1
Chih Lin 1
Tao Feng 1
Syed Suhaib 1
Andrei Rădulescu 1
Steven Bashford 1
András Orbán 1
Ernest Lampe 1
Ruth Bahar 1
Geneeu Jan 1
Surendra Bommu 1
Sandeep Sen 1
Yuming Chang 1
Michel Langevin 1
Thomas Schlichter 1
Rok Sosic 1
Juichin Chu 1
Andrew Huber 1
ChihDa Chien 1
Charles Alpert, 1
YiCheng Ho 1
Sanjiv Narayan 1
Jacopo Panerati 1
Minsik Cho 1
Tsuyoshi Abe 1
Parthasarathi Dasgupta 1
Farid Najm 1
Bo Liu 1
Georges Gielen 1
Pedro Morgado 1
Yiping Fan 1
Shihyi Yuan 1
Joseph Demaio 1
Yuan Xie 1
Le Zhang 1
Laurent Fournier 1
Wuan Kuo 1
Daniel Blakely 1
Reiner Hartenstein 1
Marco Sgroi 1
Narender Hanchate 1
Dannyziyi Chen 1
Christos Papachristou 1
Rainer Dömer 1
Duo Li 1
Lei Jiang 1
Peng Yang 1
Trevor Hodges 1
Hiroto Yasuura 1
I Tsai 1
David Landis 1
Maogang Wang 1
Incheol Park 1
Gernot Koch 1
Riccardo Scarsi 1
Yuke Wang 1
Fei Xia 1
Anand Sivasubramaniam 1
Rajib Nath 1
Yenjen Chang 1
Wei Wang 1
Michael Tian 1
Charles Wen 1
Poyang Hsu 1
Chihong Hwang 1
Wim Meeus 1
Jianbo Li 1
Debjit Pal 1
Fady Abouzeid 1
Vaughn Betz 1
Marc Renaudin 1
Rajdeep Bondade 1
Naveed Sherwani 1
Yuchun Ma 1
Sheqin Dong 1
Bo Wang 1
Karim Khordoc 1
Shianling Wu 1
Jiwon Hahn 1
Takkei Lam 1
Chiaheng Tu 1
Mahshid Roumi 1
John Havlicek 1
TzuYin Lin 1
Thanos Stouraitis 1
MingChing Lu 1
Lipin Chang 1
Chifeng Li 1
Venkataraman Mahalingam 1
ChiaoChen Fang 1
Upavan Gupta 1
Bernd Becker 1
Jeonghun Cho 1
Ritayu Chen 1
Yuki Kobayashi 1
Masaharu Imai 1
Fei He 1
Gerhard Dueck 1
David Miller 1
Peter Vanbroekhoven 1
Jiliang Zhang 1
Eddie Cheng 1
Christian Buckl 1
Kamel Beznia 1
Hongyu Chen 1
Franz Franchetti 1
Pengchih Wang 1
Yumin Kuo 1
Charles Chiang 1
Walid Najjar 1
Partha Biswas 1
Bin Xiao 1
Jason Oberg 1
Baolei Mao 1
Anche Cheng 1
Sam Bayless 1
Bojan Maric 1
Seungcheol Baek 1
Chrysostomos Nicopoulos 1
Alexander Veidenbaum 1
Chieh Changfan 1
Gong Chen 1
Chelun Hsu 1
Shigetoshi Nakatake 1
Fujiang Lin 1
Sungkwang Lee 1
Nima Darav 1
Hossein Mehri 1
Keheng Huang 1
Kan Xiao 1
Cheng Wang 1
Joseph Ganley 1
Martin Streubühr 1
Jens Gladigau 1
Michael Meredith 1
Brady Hunsaker 1
Juan Hamers 1
Brett Meyer 1
Richard Raimi 1
Duo Liu 1
Jun Matsushima 1
Shigeki Ohbayashi 1
Andrew Kennings 1
Érika Cota 1
Marcelo Lubaszewski 1
Rafael Rosales 1
William Song 1
Nicolas Blanc 1
Yu Cao 1
Sobhanbabu Ch 1
Bowen Zheng 1
Ye Zhang 1
Changhao Yan 1
Xuan Zeng 1
Fabian Oboril 1
Chen Huang 1
Joonho Kong 1
George Kornaros 1
Gilberto Ochoa-Ruiz 1
Richard Lasslop 1
Jens Vygen 1
Qing Wu 1
M Joseph 1
John Jose 1
Yenpo Ho 1
Dani Tannir 1
Matthias Kauer 1
Hassan Ghasemzadeh 1
William Lee 1
Srinivas Shakkottai 1
Fangming Ye 1
Srijan Kumar 1
Jaiming Lin 1
Ganapathy Parthasarathy 1
Smita Krishnaswamy 1
A Abbasian 1
Kyungsoo Lee 1
Mengchiou Wu 1
Guanying Wu 1
Xubin He 1
Seher Kiziltepe 1
Xi Chen 1
Sunwook Kim 1
Seiji Kajihara 1
Kohei Miyase 1
Michael Gössel 1
Weiping Shi 1

Affiliation Paper Counts
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
Macau University of Science and Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
Huawei Technologies Co., Ltd. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
North China Electric Power University 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Microsoft Research 1
University of Potsdam 1
Beijing University of Chemical Technology 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of Central Florida 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Lancaster University 1
Oak Ridge National Laboratory 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers, The State University of New Jersey 1
Nortel Networks 1
Institute of Computing Technology Chinese Academy of Sciences 1
Curtin University of Technology, Perth 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Gonzaga University 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
Lebanese American University 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Texas at San Antonio 1
University of Manchester 1
Universite de Bretagne-Sud 1
China National Petroleum Corporation 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
University of Kansas 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
University of Kaiserslautern 1
Nanjing University of Science and Technology 1
University of Kent 1
Auburn University 1
Oakland University 1
INRIA Rhone-Alpes 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Kwangwoon University 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Chengdu University of Information Technology 1
Washington State University Tri-Cities 1
National Taipei University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
Advanced Micro Devices, Inc. 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
East China Normal University 1
Villanova University 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Bar-Ilan University 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
University of Houston 2
Universitat Politecnica de Catalunya 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
Silesian Polytechnic University, Gliwice 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Indian Institute of Technology, Guwahati 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
Michigan Technological University 2
University of Tubingen 2
Southern Methodist University 2
Washington State University Pullman 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Alcatel-Lucent 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institute for Research in IT and Random Systems 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
Indian Institute of Technology Roorkee 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Korea University 3
Bogazici University 3
Delft University of Technology 3
Kitakyushu University 3
The University of Hong Kong 3
Hong Kong University of Science and Technology 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
New York University 3
Portland State University 3
Hanyang University 3
University of Brasilia 3
Stony Brook University 3
University of Melbourne 3
University of Pisa 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
University of Seville 3
University of Cyprus 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
Louisiana State University 4
Chung Hua University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Peking University 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
Swiss Federal Institute of Technology, Zurich 4
Microsoft 4
IBM Austin Research Laboratory 4
University of Milan 4
Syracuse University 4
Universite de Rennes 1 4
Pohang University of Science and Technology 4
Hunan University 4
University of Dortmund 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
Western Michigan University 5
Royal Institute of Technology 5
University of Calgary 5
Instituto Superior Tecnico 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
RWTH Aachen University 5
National University of Singapore 5
University of Bristol 5
University of North Texas 5
Agilent Technologies 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Nanjing University 5
Fujitsu America, Inc. 5
New York University Abu Dhabi 5
Universite Grenoble Alpes 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
Zhejiang University 6
North Carolina State University 6
University of Illinois 6
Fudan University 6
Brown University 6
University of California, Davis 6
Holst Centre 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
National Taiwan University of Science and Technology 6
Swiss Federal Institute of Technology, Lausanne 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
Universidade de Lisboa 6
University of Minnesota System 7
Linkoping University 7
HP Labs 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
University of California, Santa Cruz 7
Shanghai Jiaotong University 7
State University of Campinas 7
Utah State University 7
McGill University 8
Iowa State University 8
University of Electronic Science and Technology of China 8
Nanyang Technological University 8
Northwestern University 8
Federal University of Santa Catarina 8
Indian Institute of Technology, Madras 8
University of Bologna 8
Southern Illinois University at Carbondale 8
University of Wisconsin Madison 8
Indian Institute of Technology, Delhi 8
Karlsruhe Institute of Technology 8
Ulsan National Institute of Science and Technology 8
University of Michigan 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
Drexel University 9
Fuzhou University 9
Technical University of Munich 9
Freescale Semiconductor 9
University of Connecticut 9
National Central University Taiwan 9
University of Freiburg 9
University of Illinois at Chicago 9
The University of British Columbia 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
Indian Statistical Institute, Kolkata 10
University of Utah 10
Broadcom Corporation 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
Chung Yuan Christian University 10
NEC Corporation 10
Princeton University 11
Yuan Ze University 11
University of Massachusetts Amherst 11
Imperial College London 11
University of Notre Dame 11
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
University of Florida 12
University of Waterloo 12
National University of Defense Technology China 12
Korea Advanced Institute of Science & Technology 12
Samsung Electronics 13
University of Texas at Dallas 13
University of Tehran 13
University of Patras 13
University of South Florida Tampa 14
Academia Sinica Taiwan 14
University of Science and Technology of China 14
Catholic University of Leuven 14
Complutense University of Madrid 14
National Chung Cheng University 15
University of California, Berkeley 15
University of Southern California 15
Chinese Academy of Sciences 16
University of Arizona 17
University of Erlangen-Nuremberg 18
IBM 18
Cadence Design Systems 18
Ghent University 18
Virginia Tech 19
Pennsylvania State University 20
Arizona State University 20
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
University of California, Santa Barbara 21
Tsinghua University 24
National Cheng Kung University 25
University of Maryland 26
Eindhoven University of Technology 26
Synopsys Incorporated 28
Chinese University of Hong Kong 30
Duke University 31
Intel Corporation 31
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
University of Texas at Austin 35
Purdue University 36
University of Pittsburgh 37
Carnegie Mellon University 40
National Taiwan University 42
University of California, San Diego 43
National Chiao Tung University Taiwan 44
University of California, Riverside 44
Indian Institute of Technology, Kharagpur 45
Texas A and M University 51
University of California, Irvine 63
University of California, Los Angeles 65
Seoul National University 67
National Tsing Hua University 68

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Volume 22 Issue 1, November 2016  Issue-in-Progress
Volume 21 Issue 4, September 2016
Volume 21 Issue 3, July 2016 Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
Volume 21 Issue 2, January 2016

Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Volume 20 Issue 3, June 2015
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Volume 20 Issue 1, November 2014
Volume 19 Issue 4, August 2014
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Volume 19 Issue 1, December 2013
Volume 18 Issue 4, October 2013 Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Volume 18 Issue 3, July 2013
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Volume 17 Issue 4, October 2012
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Volume 17 Issue 2, April 2012
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Volume 16 Issue 4, October 2011
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Volume 16 Issue 1, November 2010
Volume 15 Issue 4, September 2010
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Volume 15 Issue 1, December 2009
Volume 14 Issue 4, August 2009
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Volume 13 Issue 4, September 2008
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Volume 12 Issue 4, September 2007
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Volume 10 Issue 4, October 2005
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Volume 9 Issue 4, October 2004
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Volume 8 Issue 4, October 2003
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Volume 7 Issue 4, October 2002
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Volume 6 Issue 4, October 2001
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Volume 5 Issue 4, Oct. 2000
Volume 5 Issue 3, July 2000
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Volume 4 Issue 4, Oct. 1999
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Volume 3 Issue 4, Oct. 1998
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Volume 3 Issue 1, Jan. 1998

Volume 2 Issue 4, Oct. 1997
Volume 2 Issue 3, July 1997
Volume 2 Issue 2, April 1997
Volume 2 Issue 1, Jan. 1997

Volume 1 Issue 4, Oct. 1996
Volume 1 Issue 3, July 1996
Volume 1 Issue 2, April 1996
Volume 1 Issue 1, Jan. 1996
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