ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the... (more)


With the emergence of many-core multiprocessor system-on-chips (MPSoCs), on-chip networks are facing serious challenges in providing fast communication among various tasks and cores. One promising on-chip network design approach shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate... (more)

Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis

In this article, we present a novel methodology based on SMT-solvers to verify equality of a high-level described specification and a pipelined RTL... (more)

Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models

Model-based design using Synchronous Reactive (SR) models enables early design and verification of application functionality in a platform-independent... (more)

Reducing the Complexity of Dataflow Graphs Using Slack-Based Merging

There exist many dataflow applications with timing constraints that require real-time guarantees on safe execution without violating their deadlines.... (more)

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration

Flash memory is widely used in mobile phones to store contact information, application files, and other types of data. In an operating system, the... (more)

An Elastic Mixed-Criticality Task Model and Early-Release EDF Scheduling Algorithms

Many algorithms have recently been studied for scheduling mixed-criticality (MC) tasks. However, most existing MC scheduling algorithms guarantee the... (more)

Computation of Seeds for LFSR-Based n-Detection Test Generation

This article describes a new procedure that generates seeds for LFSR-based test generation when the goal is to produce an n-detection test set. The... (more)

Scale 8 Cap

As the number of cores per server node increases, designing multi-threaded applications has become essential to efficiently utilize the available hardware parallelism. Many application domains have started to adopt multi-threaded programming; thus, efficient management of multi-threaded applications has become a significant research problem.... (more)

Secure and Flexible Trace-Based Debugging of Systems-on-Chip

This work tackles the conflict between enforcing security of a system-on-chip (SoC) and providing observability during trace-based debugging. On one... (more)

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for... (more)

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems

In Model-Driven Engineering system-level approaches, the design of communication protocols and patterns is subject to the design of processing... (more)


Best Paper Award: Congratulations to Chung-Wei Lin, Bowen Zheng, Qi Zhu, and Alberto Sangiovanni-Vincentelli on receiving the 2016 ACM TODAES Best Paper Award for their article titled Security-Aware Design Methodology and Optimization for Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1, Article 18, November 2015.

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

Forthcoming Articles

Special Section: Integrating Dataflow, Embedded computing and Architecture

Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices

Commercial off-the-shelf (COTS) reconfigurable devices have been recognized as one of the most suitable processing devices to be applied in nano-satellites, since they can satisfy and combine their most important requirements, namely processing performance, reconfigurability and low cost. However, COTS reconfigurable devices, in particular Static-RAM Field Programmable Gate Arrays (FPGAs), can be affected by cosmic radiation, compromising the overall nano-satellite reliability. Scrubbing has been proposed as a mechanism to repair faults in configuration memory. However, the current scrubbing mechanisms are predominantly static, unable to adapt to heterogeneous applications and their run-time variations. In this paper, a dynamically adaptive scrubbing mechanism is proposed. Through a window-based scrubbing scheduling, this mechanism adapts the scrubbing process to heterogeneous applications (composed by periodic/sporadic and streaming/DSP tasks), as well as their reconfigurations and modifications at runtime. Conducted simulation experiments show the feasibility and the efficiency of the proposed solution in terms of system reliability and memory overhead.

Worst-case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-time Tasks

In this paper, we propose a novel technique that estimates a tight upper bound of worst case response time (WCRT) of a synchronous dataflow (SDF) graph when the SDF graph shares processors with other real time tasks. When an SDF graph is executed at run-time under a self-timed or static assignment scheduling policy on a multi-processor system, static scheduling of the SDF graph does not guarantee the satisfaction of the latency constraint since the timing anomaly behavior may happen. To estimate the WCRT of an SDF graph with a given mapping and scheduling result, we first construct a task instance dependency graph (TIDG) that depicts the dependency between node executions in a static schedule. The proposed technique combines two techniques in a novel way: schedule time bound analysis (STBA) and response time analysis (RTA). The former is used to consider the interference between task instances in the same SDF graph, and the latter is used to consider the interference from other real-time tasks. Based on the proposed WCRT analysis technique, in addition, we propose a genetic algorithm (GA) based framework to solve a design space exploration problem that aims to accommodate the maximum number of real time tasks in a given hardware platform. Through extensive experiments with synthetic examples and benchmarks, we verify the superior performance of the proposed technique compared to other existent techniques.

Multiprocessor Scheduling of a Multi-mode Dataflow Graph Considering Mode Transition Delay

Synchronous Data Flow (SDF) model is widely used for specifying signal processing or streaming applications. Since modern embedded applications become more complex with dynamic behavior changes at run-time, several extensions of the SDF model have been proposed to specify the dynamic behavior changes while preserving static analyzability of the SDF model. They assume that an application has a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. They are classified as multi-mode dataflow models in this paper. While there exist several scheduling techniques for multi-mode dataflow models, no one allows task migration between modes. By observing that the resource requirement can be additionally reduced if task migration is allowed, we propose a multiprocessor scheduling technique of a multi-mode dataflow graph considering task migration between modes. Based on a genetic algorithm, the proposed technique schedules all SDF graphs in all modes simultaneously to minimize the resource requirement. To satisfy the throughput constraint, the proposed technique calculates the actual throughput requirement of each mode and the output buffer size for tolerating throughput jitter. We compare the proposed technique with a method which analyzes SDF graphs in each execution mode separately and a method that does not allow task migration for synthetic examples and three real applications: H.264 decoder, vocoder, and LTE receiver algorithms.

Approximate Energy-Efficient Encoding for Serial Interfaces

Serial buses are ubiquitous interconnections in embedded computing systems that are used to interface processing elements with peripherals, such as sensors, actuators and I/O controllers. In spite of their limited wiring, as off-chip connections they can account for a significant amount of the total power consumption of a system-on-chip device. Encoding the information sent on these buses is the most intuitive and affordable way to reduce their power contribution; moreover, the encoding can me made even more effective by exploiting the fact that many embedded applications can tolerate intermediate approximations without a significant impact on the final quality of results, thus trading off accuracy for power consumption. We propose a simple yet very effective approximate encoding for reducing dynamic energy in serial buses. Our approach uses differential encoding as a baseline scheme, and extends it with bounded approximations to overcome the intrinsic limitations of differential encoding for data with low temporal correlation. We show that the proposed scheme, besides yielding extremely compact codecs, is superior to all state-of-the-art approximate serial encodings over a wide set of traces representing data received or sent from/to sensor or actuators.

SSAGA: SMs Synthesized for Asymmetric GPGPU Applications

Emergence of GPGPU applications, bolstered by flexible GPU programming platforms, has created a tremendous challenge in maintaining a high energy efficiency in modern GPUs. In this paper, we demonstrate that, customizing a Streaming Multiprocessor (SM) of a GPU, at a lower frequency, is significantly more energy efficient, compared to employing DVFS on an SM, designed for a high frequency operation. Using a system level CAD technique, we propose SSAGAStreaming Multiprocessors Sculpted for Asymmetric GPGPU Applications, an energy efficient GPU design paradigm. SSAGA creates architecturally identical SM cores, customized for different voltage-frequency domains. Our rigorous cross-layer methodology demonstrates an average of 20% improvement in energy efficiency, over a spatially multitasking GPU, across a range of GPGPU applications.

Layer Assignment of Escape buses with Consecutive Constraints in PCB Designs

It is known that it is important for cost and reliability consideration to minimize the number of the used layers and assign the escape buses onto the available layers in a PCB design. In this paper, given a set of n escape buses between two adjacent components and a set of m consecutive constraints on the escape buses, the problem of assigning the given escape buses between two adjacent components onto the available layers is formulated in bus-oriented escape routing. Furthermore, an efficient approach is proposed to minimize the number of the used layers for the given escape buses with the consecutive constraints and assign the escape buses onto the available layers. Compared with Yans approach [J. T. Yan et al. 2012] for the layer assignment of the linear escape buses with no consecutive constraint and Mas approach [Q. Ma, F. Y. Young et al. 2011] for the layer assignment of the circular escape buses with consecutive constraints, the experimental results show that our proposed approach obtains betterl results on the number of the used layers and reduces 43.6% and 90.5% of CPU time for the tested examples on the average, respectively.

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce scan-based tests with one or more functional capture cycles between a scan-in and a scan-out operation. The approach to test generation referred to as transparent-scan has several advantages in this context. (1) It allows functional capture cycles and scan shift cycles to be interleaved arbitrarily. This increases the flexibility to assign to the scan cells values that are needed for diagnosis. (2) Test generation under transparent-scan considers a circuit model where the scan logic is included explicitly. Consequently, the test generation procedure takes into consideration the full effect of a scan chain fault. It thus produces accurate tests. (3) For the same reason it can also target faults inside the scan logic. (4) Transparent-scan results in compact test sequences. Compaction is important because of the large volumes of fail data that scan chain faults create. The cost of transparent-scan is that it requires simulation procedures for sequential circuits, and that arbitrary sequences would be applicable to the scan select input. Motivated by the advantages of transparent-scan, and the importance of diagnosing scan chain faults, this paper describes a procedure for generating transparent-scan sequences for diagnosis of scan chain faults. The procedure is also applied to produce transparent-scan sequences for diagnosis of faults inside the scan logic.

HoPE: Hot-cacheline Prediction for Dynamic Early Decompression in Compressed LLCs

Data compression plays a pivotal role in improving system performance and reducing energy consumption, because it increases the logical effective capacity of a compressed memory system without physically increasing the memory size. However, data compression techniques incur some cost, such as non-negligible compression and decompression overhead. This overhead becomes more severe if compression is used in the cache. In this paper, we aim to lower the read-hit decompression penalty, which significantly increases the cache memory access latency. We demonstrate that the speculative decompression of frequently used cachelines can significantly reduce the read-hit decompression penalty. We hereby propose a Hot-cacheline Prediction and Early decompression (HoPE) mechanism to determine when a compressed cacheline should be decompressed, in order to minimize the total execution time of the system. Additionally, we show that cachelines of similar compressibility often have a high correlation in their hit rates, as data with similar structures is often used in similar ways. Building on this insight, we also propose a compressed cacheline Hit-history-Based Insertion (HBI) policy to take advantage of this correlation, by predicting how often a cacheline will be hit, based on its compressibility. To evaluate the effectiveness of the proposed HoPE mechanism, we run extensive simulations on memory traces obtained from multi-threaded benchmarks running on a full-system simulation framework. We observe significant performance improvements over compressed cache schemes employing the conventional Least-Recently Used (LRU) replacement policy, the Dynamic Re-Reference Interval Prediction (DRRIP) scheme, and the ECM compressed cache management mechanism. Specifically, HoPE exhibits system performance improvements of approximately 11%, on average, over LRU, 8% over DRRIP, and 7% over ECM, by reducing the read-hit decompression penalty by around 65%, over a wide range of applications.

Topological Approach to Automatic Symbolic Macromodel Generation for Analog ICs

In the field of analog integrated circuit design, small-signal macromodels play indispensable roles. However, the subject of automatically generating symbolic low-order macromodels in human readable circuit form has not been well studied. Traditionally, work has been published on reducing full-scale symbolic transfer functions to simpler forms, but without the guarantee of interpretability. In this work a topological reduction method is introduced which is able to automatically generate interpretable macromodel circuits in symbolic form; that is, the circuit elements in the compact model maintain analytical relations of the parameters of the original full circuit. This type of symbolic macromodel has several benefits that other traditional modeling methods do not offer: firstly, reusability, namely, designer need not repeatedly generate macromodels for the same analog integrated circuit when it is either resized or rebiased; secondly, interpretability, namely, designer may identify directly circuit parameters in the original integrated circuit that are closely related to the dominant frequency characteristics, such as dc gain, gain/phase margins, and dominant poles/zeros, etc. The effectiveness and computational efficiency of the proposed method have been validated by several operational amplifier (opamp) circuit examples.

Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control

To alleviate high energy dissipation of unnecessary snooping accesses, snoop filter designs have been proposed to reduce snoop lookups. These filters have the problem of decreasing filtering efficiency, and thus usually rely on partial or whole filter reset by detecting block evictions. Unfortunately, the reset conditions occur infrequently or unevenly (named as passive filter deletion). This work proposes the concept of revitalized snoop filter (RSF) design, which can actively renew the destination filter by employing a generation wrapping around scheme for various reference behaviors. We further utilize a sampling mechanism for RSF to timely trigger precise filter revitalizations, so that unnecessary RSF flushing can be minimized. The proposed RSF can be integrated to various inclusive snoop filters and needs only minor change to their designs. We evaluate our proposed design and demonstrate that RSF eliminates 58.6% of snoop energy compared to JETTY on average while inducing only 6.5% of revitalization energy overhead. In addition, RSF eliminates 45.5% of snoop energy compared to stream registers on average and only induces 2.5% of revitalization energy overhead. Overall, these RSFs reduce the total L2 cache energy consumption by 52.1% (58.6%-6.5%) as compared to JETTY and by 43% (45.5%-2.5%) as compared to stream registers. Furthermore, RSF improves the overall performance by 1% to 1.4% on average compared to JETTY and Stream Registers for various benchmark suites.

A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs

Heterogeneous MPSoCs typically integrate diverse cores, including application CPUs, GPUs, and HD coders. These cores commonly share an off-chip memory to save cost and energy, but their memory accesses often interfere with each other, leading to undesirable consequences like a slowdown of application performance or a failure to sustain real-time performance. The memory controller plays a central role in meeting the QoS needs of real-time cores while maximizing the CPU performance. Previous QoS-aware memory controllers are based on a classic two-tier queuing architecture that buffers memory transactions at the first tier, followed by a second tier that buffers translated DRAM commands. In these designs, QoS-aware policies are used to schedule competing transactions at the first stage, but the translated DRAM commands are serviced in FIFO order at the second stage. Unfortunately, once the scheduled transactions have been forwarded to the command stage, newly arriving transactions that may be more critical cannot be serviced ahead of those translated commands that are already queued at the second stage. To address this, we propose a scalable memory controller architecture based on Single-Tier Virtual Queuing (STVQ) that maintains a single-tier of request queues and employs an efficacious scheduler that considers both QoS requirements and DRAM bank states. In comparison with previous QoS-aware memory controllers, the proposed STVQ memory controller reduces CPU slowdown by up to 13.9% while satisfying all frame rate requirements. We propose further optimizations that can significantly increase row-buffer hits by up to 66.2% and reduce memory latency by up to 19.8%.

A List of Fundamental Challenges Towards Making IoT a Reachable Reality: A Model-centric Investigation

The constantly advancing integration capability is paving the way to the construction of extremely large scale continuum of internet where entities, or things, from vastly varied domains are uniquely address- able and interacting seamlessly to form a giant networked system of systems, known as Internet-of-things (IoT). In contrast to such visionary networked system paradigm, prior research efforts on IoT are still very fragmented and confined to disjoint explorations in different application, architectural, security, services, protocol and economical domains, thus preventing the design exploration and optimization from a unified and global perspective. In this context, this survey article first proposes a mathematical modeling frame- work that is rich in expressivity to capture the IoT characteristics from a global perspective. Then a list of fundamental challenges in i) sensing , ii) decentralized computation, iii) energy-efficiency and iv) hardware security is identified and formulated based on the proposed modeling framework. The solutions are discussed to shed lights on future IoT system paradigm development.

Low-Power Clock Tree Synthesis for 3D-ICs

We propose efficient algorithms to construct low-power clock tree for through-silicon-via (TSV) based 3D-ICs. We use shutdown gates to save clock tree's dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering. (2) Clock tree embedding with simultaneous shutdown gates insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that: (1) The K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity. (2) The SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis technique, our K-means clustering based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

Optimal Scheduling and Allocation for IC Design Management and Cost Reduction

A large semiconductor product company spends hundreds of millions of dollars each year on design infrastructure to meet tapeout schedules for multiple concurrent projects. Resources (servers, EDA tool licenses, engineers, etc.) are limited and must be shared  and the cost per day of schedule slip can be enormous. Co-constraints between resource types (e.g., one license per every two cores (threads)) and dedicated versus shareable resource pools make scheduling and allocation hard. In this paper, we formulate two mixed integer-linear programs for optimal multi-project, multi-resource allocation with task precedence and resource co-constraints. Application to a real-world three-project scheduling problem extracted from a leading-edge design center of anonymized Company X shows substantial compute and license costs savings. Compared to the product company, our solution shows that the makespan of schedule of all projects can be reduced by seven days, which not only saves ~2.7% of annual labor and infrastructure costs, but also enhances market competitiveness. We also demonstrate the capability of scheduling over two dozen chip development projects at the design center level, subject to resource and datacenter capacity limits as well as per-project penalty functions for schedule slips. The design center ended up purchasing 600 additional servers, whereas our solution demonstrates that the schedule can be met without having to purchase any additional servers. Application to a four-project scheduling problem extracted from a leading-edge design center in a non-U.S. location shows availability of up to ~37% headcount reduction during a half-year schedule for just one type of chip design activity.

A Fast Hierarchical Adaptive Analog Routing Algorithm based on Integer Linear Programming

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges to the analog and RF integrated circuit designers. The state-of-the-art analog routing research tends to favor linear programming to achieve various analog constraints, which, although effective, fails to offer high routing efficiency on its own. In this paper, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Our proposed method supports hierarchical routing, which can divide the entire routing area into multiple small heterogeneous regions where the ILP can efficiently derive routing solutions. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. For a large empty space, routing efficiency can be even boosted by creating more routing hierarchy levels. This scheme is especially beneficial to the analog and RF layouts, which are far sparser than the digital counterpart. The experimental results show that our proposed adaptive ILP-based router is much faster than the conventional ones since it spends much less time for the areas that need no accurate routing anyway. The high efficiency is demonstrated for large circuits and especially sparse layouts along with promising routing quality in terms of analog constraints.

PeaPaw: Performance and Energy Aware Partitioning of Workload on Heterogeneous Platforms

Performance and energy are two major concerns for application development on heterogeneous platforms. It is challenging for application developers to fully exploit the performance/energy potential of heterogeneous platforms. One reason is the lack of reliable prediction of the system's performance/energy before application implementation. Another reason is that a heterogeneous platform presents a large design space for workload partitioning between different processors. To reduce such development cost, this paper proposes a framework, PeaPaw, to assist application developers to identify a workload partition (WP) that has high potential leading to high performance or energy efficiency before actual implementation. The PeaPaw framework includes both analytical performance/energy models and two sets of workload partitioning guidelines. Based on the design goal, application developers can obtain a workload partitioning guideline from PeaPaw for a given platform and then follow it to design one or multiple WPs for a given workload. Then PeaPaw can be used to estimate the performance or energy of the designed WPs, and the WP with the best estimated performance or energy will be selected for further implementation. To demonstrate the effectiveness of PeaPaw, we have conducted three case studies. Results from these case studies show that PeaPaw can faithfully estimate the performance/energy relationships of WPs and provide effective workload partitioning guidelines.

Application-Specific Residential Microgrid Design Methodology

In power system industry, the traditional, non-interactive, and manually-controlled power grid has been transformed to cyber-dominated smart grid. This cyber-physical integration has provided the smart grid with communication, monitoring, computation, and controlling capabilities to improve its reliability, energy efficiency, and flexibility. A microgrid as a localized and semi-autonomous group of smart energy systems, utilizes the above-mentioned capabilities to drive modern technologies such as electric vehicle charging, home energy management, smart appliances, etc. Designing, upgrading, testing, and verifying these microgrids can get too complicated to handle manually. The complexity is due to the wide range of solutions and components that are intended to address the microgrid problems. This paper presents a novel Model-Based Design (MBD) methodology to model, co-simulate, design, and optimize microgrid and its multi-level controllers. It helps us to design, optimize, and validate a microgrid for a specific application. The application rules, requirements, and design-time constraints are met in the designed/optimized microgrid while the implementation cost is minimized. Based on our novel methodology, a design automation, co-simulation, and analysis tool, called GridMAT, is implemented. Our experiments have illustrated that implementing a hierarchical controller reduces the average power consumption by 8% and shifts the peak load for cost saving. Moreover, using our MBD methodology with smart controllers, the total implementation cost decreases by 14%, when upgrading a microgrid, compared to the conventional methodology and 5%, compared to the case where smart controllers are not considered.

Using CoreSight PTM to integrate CRA monitoring IPs in an ARM-based SoC

ARM CoreSight PTM has been widely deployed in recent ARM processors for real-time debugging and tracing of software. Using PTM, the external debugger can extract execution behaviors of applications running on an ARM processor. Recently, some researchers begin to use this feature for other purposes such as fault tolerant computation and security monitoring. This motivated us to develop an external security monitor that can detect control hijacking attacks, of which goal is to maliciously manipulate the control flow of victim applications at attackers disposal. Especially, this paper focuses on detecting a special type of attacks, called code reuse attacks (CRA), which uses a recently-introduced technique that allows attackers to perform arbitrary computation without injecting their code by reusing only the existing code fragments. Our external monitor is attached to the outside of the host system via the system bus and ARM CorSight PTM, and fed with execution traces of a victim application running on the host. As a majority of CRAs violates the normal execution behaviors of a program, our monitor constantly watches and analyzes the execution traces of the victim application and detect a symptom of attacks when the execution behaviors violate certain rules that normal applications are known to adhere. We present two different implementations for this purpose; a hardware-based solution in which all the CRA detection components are implemented in hardware, and a hardware/software mixed solution that can be employed in more resource constrained environment where the deployment of the full hardware level CRA detection is burdensome.

Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits

Radiation-induced soft errors have posed an increasing reliability challenge to combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise fast, accurate and scalable soft error rate (SER) estimation methods as part of cost-effective robust circuit design. This paper presents an efficient SER estimation framework for combinational and sequential circuits, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential elements. A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs, and a general schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. The feedback in sequential logic is analyzed with an efficient time frame expansion method. Experimental results on various ISCAS85 combinational benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3\% difference in terms of SER results compared with the baseline algorithm. The average runtime of the proposed framework on a variety of ISCAS89 sequential benchmark circuits is 2.535s, and the runtime is 30.429s for the largest benchmark circuit with more than 1,000 flip-flops and 20,000 gates.

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Recently, phase change memory (PCM) is emerging as a strong replacement for DRAM owing to its many advantages such as non-volatility, high scalability, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by reducing bit flips. Although they have significantly contributed to bit flip reduction, they still have the drawback that the lower bits are flipped more often than the higher bits. The reason is that these methods do not consider the fact that, in general, the lower bits are updated much more frequently than the higher bits. In this paper, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. Specifically, CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method, while consuming a few extra resources for metadata. We have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability and Authentication in IoT Supply Chain

The Internet of Things (IoT) is transforming the way we live and work by increasing the connectedness of people and things on a scale that was once unimaginable. However, the vulnerabilities in IoT supply chain have raised serious concerns about the security and trustworthiness of IoT devices and components on them. Testing for device provenance, detection of counterfeit integrated circuits (ICs) and systems, and traceability of IoT devices are challenging issues to address. In this paper, we develop a novel RFID-based system suitable for Counterfeit Detection, Traceability and Authentication in IoT supply chain called CDTA. CDTA is composed of different types of on-chip sensors and in-system structures that collect necessary information to detect multiple counterfeit IC types (recycled, cloned, etc.), track and trace IoT devices, and verify the overall system authenticity. Central to CDTA is an RFID tag employed as storage and a channel to read the information from different types of chips on the printed circuit board (PCB) in both power-on and power-off scenarios. A novel board ID generator is implemented by combining outputs of physical unclonable functions (PUFs) embedded in RFID tag and different chips on the PCB. A light-weight RFID protocol is proposed to enable mutual authentication between RFID readers and tags. We also implement a secure inter-chip communication on the PCB. Simulations and experimental results using Spartan 3E FPGAs demonstrate the effectiveness of this system. The efficiency of the radio frequency (RF) communication has also been verified via a PCB prototype with a printed slot antenna.

Temperature Effect Inversion Aware Dynamic Thermal Management for FinFET Circuits

Due to the superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the gate delay vs. temperature characteristics of FinFET circuits may be fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Fur- thermore, with the optimal buffer insertion, we have observed that interconnect delay of the FinFET circuits may follow the same trend for the temperature change. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET circuits without any appreciable performance penalty. Experi- mental results demonstrate that significant energy saving (as high as 36%, with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencie

This works presents a Design Space Exploration (DSE) method for Behavioral IPs (BIPs) given in ANSI-C or SystemC in order to find the smallest micro-architecture for a specific target latency. Previous work on High-Level Synthesis (HLS) DSE mainly focused on finding a trade-off curve with Pareto-optimal designs. HLS is however a single process (component) synthesis method. Very often, the latency of the components requires a specific fixed latency when inserted within a larger system. This work presents a fast multi-threaded method to find the smallest micro-architecture for a given BIP and target latency, by discriminating between all different exploration knobs and exploring these concurrently. Experimental results shows that our propose method is very effective and comprehensive results compare the quality of results vs. the speedup of your proposed explorer.

A Survey of Parametric Dataflow Models of Computation

Dataflow models of computation (MoCs) are widely used to design embedded signal processing and streaming systems. Dozens of dataflow MoCs have been proposed in the few last decades. More recently, several parametric dataflow MoCs have been presented as an interesting trade-off between analyzability and expressiveness. The dynamism is controlled and takes the form of parameters (e.g., parametric rates) and run-time parameter configuration. This paper first strives to formalize or clarify criteria used to compare dataflow MoCs. It then provides a comprehensive description of the existing parametric dataflow MoCs (constructs, constraints, properties, static analyses) which may help designers of streaming applications to choose the most suitable model for their needs.


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First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Distinguished Member (2008)
ACM Senior Member (2006)
Naehyuck Chang ACM Distinguished Member (2012)
ACM Senior Member (2007)
Danny Z Chen ACM Distinguished Member (2014)
ACM Senior Member (2011)
Nikil D. Dutt ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
Soheil Ghiasi ACM Senior Member (2015)
Prosenjit Gupta ACM Senior Member (2008)
Matthew Guthaus ACM Senior Member (2013)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
John Lee ACM Senior Member (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Ian Parberry ACM Distinguished Member (2015)
Massoud Pedram ACM Distinguished Member (2008)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
Robert Schreiber ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 18
Irith Pomeranz 15
Nikil Dutt 15
Krishnendu Chakrabarty 13
Jason Cong 12
Sheldon Tan 10
Partha Chakrabarti 10
TingTing Hwang 9
Sachin Sapatnekar 9
Lei He 8
Yaowen Chang 8
Spyros Tragoudas 7
Yunheung Paek 7
Evangeline Young 7
Frank Vahid 7
Massoud Pedram 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Taewhan Kim 6
Martin Wong 6
Alexandru Nicolau 6
John Hayes 6
Bhargab Bhattacharya 6
Ryan Kastner 6
Chengkok Koh 6
Radu Marculescu 6
Sudhakar Reddy 6
Igor Markov 6
Ali Dasdan 5
Sule Ozev 5
Sharad Malik 5
David Pan 5
Ramesh Karri 5
Kiyoung Choi 5
Kaushik Roy 5
Mahmut Kandemir 5
Umit Ogras 5
Jenqkuen Lee 5
Preeti Panda 5
Rajeev Kumar 5
Aviral Shrivastava 5
Giovanni De Micheli 5
Andrew Kahng 5
Tony Givargis 5
Nagarajan Ranganathan 5
Roman Lysecky 5
Chungkuan Cheng 5
Chialin Yang 4
Kwangting Cheng 4
Rajesh Gupta 4
Zijiang Yang 4
Sunil Khatri 4
El Aboulhamid 4
Jingyang Jou 4
Aarti Gupta 4
Xiaobosharon Hu 4
Pinghung Yuh 4
Shihhsu Huang 4
Peter Petrov 4
Peng Li 4
Iris Jiang 4
Alex Jones 4
Yuanhao Chang 4
Hungming Chen 4
Sunyuan Hsieh 4
Hans Wunderlich 4
Chang Liu 4
Jintai Yan 4
Allen Wu 4
Naehyuck Chang 4
Miodrag Potkonjak 4
Paul Gratz 4
Jongeun Lee 4
Dinesh Mehta 4
Franco Fummi 4
Paulo Flores 4
Hai Zhou 4
Dirk Stroobandt 4
Zonghua Gu 4
Azadeh Davoodi 4
Shihchieh Chang 3
Xianlong Hong 3
Greg Stitt 3
Li Wang 3
Chakkuen Wong 3
Waikei Mak 3
Seda Memik 3
Yuan Xie 3
Karel Bruneel 3
Bijan Alizadeh 3
Henk Corporaal 3
Dimitrios Kagaris 3
Praveen Raghavan 3
Martin Lukasiewycz 3
Soonhoi Ha 3
Valeria Bertacco 3
Viktor Prasanna 3
Diana Marculescu 3
Jürgen Teich 3
Ronald Blanton 3
Zili Shao 3
Ozgur Sinanoglu 3
Paolo Prinetto 3
Sebastian Steinhorst 3
Paoann Hsiung 3
Sreejit Chakravarty 3
Wen Jone 3
Guangming Wu 3
Axel Jantsch 3
Janet Roveda 3
Guy Gogniat 3
Sisira Panda 3
Zoran Salcic 3
Dipankar Das 3
Prabhat Mishra 3
Masanori Kurimoto 3
Yuchin Hsu 3
Xiaoyu Song 3
Yunsi Fei 3
Anna Bernasconi 3
Ozcan Ozturk 3
Arnout Vandecappelle 3
Chenjie Yu 3
Peter Cheung 3
Costas Goutis 3
Youngsoo Shin 3
Chungwen Huang 3
Shiyu Huang 3
Karem Sakallah 3
Valentina Ciriani 3
Alberto Sangiovanni-Vincentelli 3
Mehdi Tahoori 3
Juan Maestro 3
Massimo Poncino 3
Fadi Kurdahi 3
Partha Roop 3
Tsungyi Ho 3
Gianpiero Cabodi 3
Seongnam Kwon 3
Soheil Ghiasi 3
Pai Chou 3
Sarma Vrudhula 3
Kurt Keutzer 3
Thambipillai Srikanthan 3
Yowtyng Nieh 3
Martin Palkovič 3
Pedro Reviriego 3
Daniel Gajski 3
Xiangrong Zhou 3
Yi Wang 3
Madhu Mutyam 3
David Atienza 3
Majid Sarrafzadeh 3
Per Kjeldsberg 3
Janak Patel 3
José Monteiro 3
Baris Taskin 3
Hai Wang 3
Chiuwing Sham 3
Edwin Sha 3
Domenic Forte 3
Dong Xiang 3
Yinhe Han 3
Nicholas Zamora 3
Saojie Chen 3
Priyank Kalla 3
Elizabeth Rudnick 3
Yiping You 3
Enrico Macii 3
Ankur Srivastava 3
Shuvra Bhattacharyya 3
Krishnendu Chakrabarty 3
Twan Basten 3
Teiwei Kuo 3
George Constantinides 3
Hao Yu 3
Russell Tessier 2
Maurizio Rebaudengo 2
Kiwook Kim 2
Kyumyung Choi 2
Srinivas Devadas 2
Vigyan Singhal 2
Ismail Kadayif 2
Levent Aksoy 2
Smita Bakshi 2
Siddhartha Mukhopadhyay 2
Rudy Lauwereins 2
Srinivas Katkoori 2
Andreas Dandalis 2
Guolong Chen 2
Janming Ho 2
Sudhakar Yalamanchili 2
Qinru Qiu 2
Deepak Mathaikutty 2
Robert Walker 2
Sanghamitra Roy 2
Haibao Chen 2
Gary Dispoto 2
Jun Yang 2
Cheng Wang 2
Natarajan Viswanathan 2
Román Hermida 2
Tsungyi Ho 2
Picheng Hsiu 2
Christophe Wolinski 2
Alper Sen 2
Yongjoo Kim 2
Wim Heirman 2
Dimitrios Soudris 2
Zebo Peng 2
Sivaram Gopalakrishnan 2
Jagannathan Ramanujam 2
Erik Brockmeyer 2
Inki Hong 2
Duncan Walker 2
Farinaz Koushanfar 2
Naiwen Chang 2
Masahiro Fujita 2
Chiachun Tsai 2
Chrystian Guth 2
Yuliang Wu 2
Jhihrong Gao 2
Seokhyeong Kang 2
Sarmishtha Ghoshal 2
Hafizur Rahaman 2
Koushik Chakraborty 2
Jin Sun 2
Jun Zeng 2
Haibo Zeng 2
Gregory Dimitroulakos 2
Luciano Lavagno 2
Michel Auguin 2
Min Xu 2
Freek Verbeek 2
Vijaykrishnan Narayanan 2
Michael Hsiao 2
Xuexin Liu 2
Anmol Mathur 2
Sergio Nocco 2
Zhiyu Zeng 2
Dongsheng Ma 2
Jochen Jess 2
Chiajui Hsu 2
José Pino 2
Joann Paul 2
Konstantin Moiseev 2
Jun Yang 2
Luigi Carro 2
Chingren Lee 2
Leyla Nazhandali 2
Timothy Sherwood 2
Akash Kumar 2
Swaminathan Narayanaswamy 2
Chienchih Huang 2
Chinlong Wey 2
Jwu Chen 2
Shihhao Hung 2
Wayne Wolf 2
Graziano Pravadelli 2
John Gough 2
Hai Wang 2
Mateo Valero 2
Avinash Malik 2
Jörg Henkel 2
Swarup Bhunia 2
Susmita Sur-Kolay 2
Guangyu Chen 2
Paul Thadikaran 2
Marc Boulé 2
Younlong Lin 2
C Shi 2
Yiyu Shi 2
Arnab Roy 2
Laungterng Wang 2
Xing Huang 2
Peter Milder 2
Hui Liu 2
Guihai Yan 2
Ricardo Reis 2
Siddharth Garg 2
Nicola Bombieri 2
Jiping Liu 2
Radu Marculescu 2
Puneet Gupta 2
Maria Michael 2
Mohammad Arjomand 2
Bo Zhao 2
Sujit Dey 2
James Cain 2
Leonid Mats 2
Marco Bekooij 2
Franjo Ivančić 2
Zhiwei Qin 2
Mark Tehranipoor 2
Guido Araújo 2
Fei Su 2
Abhijit Jas 2
Wayne Luk 2
P Chakrabarti 2
Matthew Guthaus 2
Gustavo Wilke 2
Julien Schmaltz 2
Markus Püschel 2
Doosan Cho 2
Jingyang Jou 2
Vinícius Livramento 2
Francesco Poletti 2
Miguel Miranda 2
Mary Irwin 2
Ingoo Heo 2
Hsiangpang Li 2
Marlin Mickle 2
Hiroaki Inoue 2
Kanupriya Gulati 2
Sudip Roy 2
Luís Silveira 2
Vivek Sarin 2
Ali Afzali-kusha 2
Yiyu Liu 2
Deming Chen 2
José Mendías 2
Ronald Graham 2
M Balakrishnan 2
Stan Liao 2
Mike Lee 2
Ansuman Banerjee 2
Sreeranga Rajan 2
Avinoam Kolodny 2
Erik Marinissen 2
Michael Kochte 2
Genggeng Liu 2
Wenzhong Guo 2
Meeta Srivastav 2
Bart Mesman 2
Muhammet Ozdal 2
Samarjit Chakraborty 2
Bei Yu 2
Peiwen Luo 2
Dawei Chang 2
Shenchih Tung 2
Mario López 2
Kun Yuan 2
Arcot Sowmya 2
Rajdeep Mukhopadhyay 2
Yiyu Shi 2
Peichen Pan 2
Chung Tsao 2
Murali Jayapala 2
Dakai Zhu 2
Swapna Dontharaju 2
Kees Goossens 2
Chinhsien Wu 2
Chao Wang 2
Masato Edahiro 2
Meikang Qiu 2
Angeliki Kritikakou 2
Aiqun Cao 2
Roberto Passerone 2
Javed Absar 2
Lei Li 2
Krzysztof Kuchcinski 2
Yvon Savaria 2
Xin Yuan 2
Peng Li 2
Shmuel Wimer 2
Rafal Baranowski 2
Bin Liu 2
Kaihui Chang 2
Pochun Huang 2
Bocheng Lai 2
José Güntzel 2
Sandeep Shukla 2
Xin Li 2
David Hély 2
Eduard Cerny 2
Jun Gu 2
Poyuan Chen 2
Junji Sakai 2
Jaume Abella 2
Sungmo Kang 2
Junjuan Xu 2
Vasilios Kelefouras 2
Sungjoo Yoo 2
Sunggu Lee 2
Chandra Suresh 2
Melvin Breuer 2
Marco Murciano 2
Xiaoping Hu 2
Manfred Glesner 2
Jim Holt 2
Magdy Abadir 2
Adnan Aziz 2
Saraju Mohanty 2
Tajana Rosing 2
Željko Žilić 2
Chunjason Xue 2
Michael Riepe 2
Stefano Quer 2
Mohammad Tehranipoor 2
Luiz Dos Santos 2
Ranga Vemuri 2
Mehrdad Nourani 2
Kai Zhu 2
Nur Touba 2
ChengHsing Yang 2
Hyesoon Kim 2
Elaheh Bozorgzadeh 2
Hongbing Fan 2
Shantanu Dutt 2
Paul Bogdan 2
Hiren Patel 2
Hsinhung Chen 2
Yongje Lee 2
Jinyong Lee 2
Qing Duan 2
Alain Girault 2
Jos Huisken 2
Chiaming Chang 2
Donald Thomas 2
S Ramesh 2
Francisco Cazorla 2
Matteo Reorda 2
Jinnshyan Wang 1
Chengyang Fu 1
Xiaoyao Liang 1
ChengTsung Hwang 1
Sudhakar Muddu 1
Alan Mishchenko 1
Shichun Tsai 1
Qiang Dou 1
Luis Bathen 1
Chienchin Huang 1
Suming Lai 1
Dionisios Pnevmatikatos 1
Dirk Muller 1
Hao Shen 1
Nadereh Hatami 1
Reeshav Kumar 1
Selvaraj Ravi 1
Reinhard Schneider 1
Peng Li 1
Mohammed Ehteshamuddin 1
Jian Liu 1
Qi Zhang 1
Sara Vinco 1
Vinay Verma 1
PoHsien Chang 1
Heejong Park 1
WeiChung Chao 1
Mahir Turkcan 1
Deming Chen 1
Jaekyu Lee 1
Kumar Parthasarathy 1
Lingling Jin 1
Pablo Del Valle 1
Giacomo Paci 1
YoungMin Yi 1
Mohamed Bechara 1
Tathagato Dastidar 1
Nikhil Saluja 1
Pinhong Chen 1
Jeff White 1
Shakith Fernando 1
Anuja Sehgal 1
Yu Cao 1
Karthik Shankar 1
Adam Postula 1
Frank Hannig 1
Song Liu 1
Lihong Zhang 1
Bipul Paul 1
ChiShong Wang 1
Robert Rogenmoser 1
Alessandro Pinto 1
Alvise Bonivento 1
Peter Jamieson 1
Nalini Venkatasubramanian 1
Evangeline Young 1
Xinping Zhu 1
Sandip Ray 1
Jaideep Dastidar 1
David Lindberg 1
Kuanyu Lin 1
Xiaotao Chen 1
Shantanu Ganguly 1
Feng Liu 1
Krishnan Srinivasan 1
Vijaykumar Ramamurthi 1
Qubo Hu 1
Pranav Ashar 1
Yuetsang Chen 1
Ismaïl Chabini 1
Kara Poon 1
Adolfo Palma-Rodriguez 1
Mark Greenstreet 1
Jingjou Tang 1
Kurt Antreich 1
JingWei Lin 1
Yeanyow Hwang 1
Eric Chio 1
Junyan Ren 1
Meihsiang Tsai 1
Yihuang Hung 1
Ernest Kuh 1
Gilles Sicard 1
Yangdong Deng 1
Yue Yu 1
Cornelis Van Eijk 1
Eric Johnson 1
Janusz Brzozowski 1
TungChieh Tsai 1
Srikanth Chandrasekaran 1
Sanghoon Kwak 1
Vivek Joshi 1
Gagan Hasteer 1
Jing Zeng 1
Xubin He 1
Sunwook Kim 1
Kohei Miyase 1
Seiji Kajihara 1
Michael Gössel 1
Weiping Shi 1
Paulo Centoducatte 1
Lei Cheng 1
Nicholas Callegari 1
Woochul Jeun 1
Youngjin Cho 1
José Gómez 1
Rance Rodrigues 1
Arunachalam Annamalai 1
Israel Koren 1
Yunghsiang Lu 1
Michael Henry 1
Jyothi Velamala 1
Chun Jason Xue 1
Xuehai Zhou 1
Kalyan Saladi 1
Mahadevan Ganapathi 1
Michael Moffitt 1
Philip Honsinger 1
Pedro Diniz 1
Zhiru Zhang 1
Montek Singh 1
Yuze Wu 1
Carlos Pinto 1
Shail Aditya 1
Avaneendra Gupta 1
Mark Aagaard 1
Edward McCluskey 1
Kedar Namjoshi 1
Wenli Shih 1
Lingyi Liu 1
Harald Søndergaard 1
Peter Stuckey 1
Chiara Sandionigi 1
Ilya Issenin 1
Arun Kejariwal 1
Wenyong Deng 1
Hassan Ghasemzadeh 1
Dani Tannir 1
Matthias Kauer 1
Ge Yu 1
Javier Resano 1
Daniel Mozos 1
KuangCyun Hsiao 1
Peter Marwedel 1
Saurabh Adya 1
Kiyin Chang 1
Ian Parberry 1
Chichou Kao 1
Heman Khanna 1
Jason Higgins 1
David Long 1
Mahesh Iyer 1
Qingfeng Zhuge 1
Sunil Chappidi 1
Yehia Massoud 1
Hyunggyu Lee 1
Jongman Kim 1
Celina Val 1
CP Ravikumar 1
Sumit Mohanty 1
Gang Quan 1
Jay Roy 1
Suman Datta 1
Ujjwal Guin 1
Chang Xu 1
Peixin Li 1
Andrew Kennings 1
Xiaoqing Xu 1
Wenchao Zhang 1
Shengxi Diao 1
Pangbo Wu 1
Ramachandran Venkatasubramanian 1
John Backes 1
Marc Riedel 1
P Bannerjee 1
Hsipin Ma 1
Peter Bertels 1
Bettina Braitling 1
Peter Middelhoek 1
Bontae Koo 1
Juan De Vicente 1
Raminder Bajwa 1
Qi Guo 1
Olivier Temam 1
Gang Qu 1
Lokwon Kim 1
John Villasenor 1
Marjan Asadinia 1
Hamid Azad 1
Tanja Van Achteren 1
I Hsu 1
Michio Komoda 1
Zhen Chen 1
Menghuan Wu 1
Shihhung Weng 1
Alan Coppola 1
Wei Jiang 1
Yu Liu 1
Tomtong Jing 1
Robi Dutta 1
Shaz Qadeer 1
Ralph Hasholzner 1
Nong Xiao 1
Stefan Hillebrecht 1
Jiantao Wang 1
Frank Vahid 1
Ankur Srivastava 1
Martin Leucker 1
Hakan Aydín 1
Renjie Lee 1
Wenpin Tu 1
Yoonseok Yang 1
Samarjit Chakraborty 1
Kyle Stegner 1
Chao Wang 1
Jongchul Lee 1
Zhonghai Lu 1
Adam Kaplan 1
Amit Singh 1
Jhengsyun Yang 1
William Lee 1
Pohsun Wu 1
Laleh Behjat 1
Haomo Tang 1
Yande Jiang 1
Srinivas Shakkottai 1
Hany Kashif 1
Claudio Talarico 1
Ying Qin 1
Shengyu Shen 1
Huadong Dai 1
Qi Zhu 1
Waishing Luk 1
Jiajia Li 1
José Pineda De Gyvez 1
Thomas Mittelholzer 1
Charles Camp 1
Yang Zheng 1
Leila Delshadtehrani 1
Hamed Farbeh 1
Weijian Su 1
Abhishek Koneru 1
Leandro Indrusiak 1
Osmar Dos Santos 1
Rajat Chakraborty 1
Di Zhu 1
Yejyun Lin 1
Lieven Eeckhout 1
James Cohoon 1
Yi Zhu 1
Hsungpin Chang 1
Lakshmi Reddy 1
Giovanni Beltrame 1
Juinndar Huang 1
Dariusz Kania 1
Yang Guo 1
He Tang 1
Chihao Chen 1
Hemangee Kapoor 1
Yunghsiang Lu 1
N Harsha 1
Sujoy Ghose 1
Sreenivas Gangadhar 1
Renhai Chen 1
Bodhisatwa Mazumdar 1
Marcelo Cintra 1
Tan Yan 1
Xiangyang Guo 1
Jeremy Dubeuf 1
Xinyu He 1
Songwei Pei 1
Ekaterina Kutsy 1
Margarida Jacome 1
Ofer Strichman 1
Shaoxi Wang 1
Kartikey Mittal 1
Michael Healy 1
André Nácul 1
Zhongzhen Wu 1
Chingwei Yeh 1
Keven Dunn 1
Stanley Baumgart 1
Saravanan Padmanaban 1
Stylianos Mamagkakis 1
Karthikeyan Lingasubramanian 1
Sandeep Gupta 1
Rajeshkumar Sambandam 1
Tobias Becker 1
Jun Seomun 1
Takayasu Sakurai 1
Xufa Wang 1
Subhashis Majumder 1
Jean Berge 1
Mohamed Elwakil 1
Chittaranjan Mandal 1
Joan Lopez 1
ChungHwang Chen 1
JyhMou Tseng 1
Gerda Janssens 1
Wenrui Gong 1
Brian DeRenzi 1
Michael Boyer 1
Srikanth Venkataraman 1
Horácio Neto 1
Joseph Shinnerl 1
Qingan Li 1
Esteban Tlelo-Cuautle 1
Klaus Eckl 1
Kuenjong Lee 1
Tsungchu Huang 1
Andrew Wolfe 1
Yau Li 1
Tienfu Chen 1
F Johnson 1
Yushih Su 1
Chaitali Chakrabarti 1
Rungbin Lin 1
Bruno Rouzeyre 1
Jongeun Lee 1
Rami Melhem 1
I Tseng 1
Chita Das 1
Sandeep Goel 1
Muhammad Nummer 1
Le Jin 1
Giovanni De Micheli 1
Choonseung Lee 1
Hasan Khalifeh 1
Fang Liu 1
Plamen Nikolov 1
Sandro Rigo 1
Max Schultz 1
Yu Hu 1
Roberto Cordone 1
Ronny Krashinsky 1
Antonis Papanikolaou 1
Tomas Pecenka 1
Lukáš Sekanina 1
Zdeněk Kotásek 1
Jennifer Dworak 1
Nuno Alves 1
Jürgen Teich 1
Rui Zheng 1
Liang Shi 1
Jianhua Li 1
Harikumar Somakumar 1
Wenyao Xu 1
Syingjyan Wang 1
Katherine Li 1
William Davis 1
Jinsik Kim 1
Hadi Esmaeilzadeh 1
Saeed Shamshiri 1
Jef Meerbergen 1
Jef Van Meerbergen 1
Rainer Leupers 1
KunLin Tsai 1
Shanqjang Ruan 1
Paolo Camurati 1
K Tsai 1
Huankai Peng 1
HsuanMing Huang 1
Chandu Visweswariah 1
Raj Nadakuditi 1
Wanting Lo 1
Chiehjui Lee 1
Shashidhar Thakur 1
Adrian Ludwin 1
Tiempo Sas 1
Yuhao Zhu 1
Wenjong Fang 1
Vincent Mooney 1
Michael Hsiao 1
James Li 1
Scott Little 1
Matthew Gately 1
Gauthier Lafruit 1
David Bild 1
Gregory Bok 1
Claudio Sansoé 1
Piet Engelke 1
Sally McKee 1
Keshab Parhi 1
Kevin Lepak 1
Michael Mefenza 1
Jingwei Lu 1
Said Hamdioui 1
Adwait Gupte 1
Nathan Denny 1
J Chen 1
William Hung 1
Sumit Gupta 1
Stephen Cauley 1
Ying Hu 1
U Rovati 1
Yufu Zhang 1
Ausif Mahmood 1
Seongook Jung 1
Stephen Edwards 1
Ali Pınar 1
Jackey Yan 1
Chris Chu 1
Yongwen Wang 1
Dominik Erb 1
Matthias Sauer 1
Tobias Schubert 1
Péter Arató 1
Donald Gelosh 1
Dorothy Setliff 1
Stephen Blythe 1
Alain Pegatoquet 1
Ramin Hojati 1
Patrick Schaumont 1
Ashok Halambi 1
Qing Su 1
Chakchung Cheung 1
Sharad Sinha 1
Alain Darte 1
B Rau 1
Sungwoo Hur 1
Ashok Jagannathan 1
Harry Hoster 1
Andreas Burg 1
Bingsheng He 1
Marcela Zuluaga 1
Shiyan Hu 1
Bo Yang 1
Guojie Luo 1
Aysa Tabrizi 1
Youjip Won 1
Prasun Ghosal 1
Myungsun Kim 1
Hyojung Lee 1
Yan Jia 1
Chungwei Lin 1
Ankit More 1
Thomas Parnell 1
Sudipta Bhawmik 1
Ludovic Apvrille 1
Renaud Pacalet 1
Adnan Bouakaz 1
Justin Stander 1
Frederik Vandeputte 1
Stelios Mamagkakis 1
Puneet Sharma 1
Arnab Sinha 1
Bhaskar Pal 1
Yuanfang Hu 1
Yubin Zhang 1
Adam Hartman 1
Daujieu Yang 1
Huihsin Hsu 1
Jenhao Chen 1
Douglas Keller 1
Jongkyung Paek 1
Enshou Chang 1
Xu He 1
Yao Wang 1
Chi Zhang 1
Megha Gandhi 1
Arnab Sarkar 1
Swarup Bhunia 1
Giovanni Squillero 1
Vikram Saxena 1
Francisco Fernández 1
Chihhung Liu 1
Syyen Kuo 1
Paul Feautrier 1
Yi Xu 1
Vincent Beroulle 1
Kele Shen 1
Zhi Li 1
Mehdi Kamal 1
Xiaobosharon Hu 1
Xiaofang Wang 1
Viktor Lapinskii 1
Gustavo De Veciana 1
Ibrahim Hajj 1
Xinzhang Jia 1
Filipa Duarte 1
Jun Zhou 1
Hsien Lee 1
Chen Li 1
Kuohua Wang 1
Ricardo Jacobi 1
Zuoyuan Li 1
Tero Rissa 1
Chris Bleakley 1
Hidehiro Takata 1
Yosinori Watanabe 1
Renshen Wang 1
Anshul Kumar 1
Swarup Das 1
Michael Münch 1
Laurent Freund 1
Mohammad Foroozannejad 1
Hassan Salamy 1
J Lee 1
Giri Tiruvuri 1
Franc Breglez 1
Michael Gasteier 1
W Fuchs 1
Ismed Hartanto 1
Kuangchien Chen 1
Koen Danckaert 1
Steven Levitan 1
Noureddine Chabini 1
Hsiangyu Lu 1
Yiran Chen 1
Bernd Wurth 1
Ulf Schlichtmann 1
Olivier Sentieys 1
Pai Chou 1
Saket Gupta 1
Sartaj Sahni 1
Jiang Hu 1
Vilasita Kuntamukkala 1
Steve Tjiang 1
Nagu Dhanwada 1
Anjur Krishnakumar 1
Andrew Cassidy 1
Hua Xiang 1
Arijit Mondal 1
Xiaoqing Wen 1
Xiaoqing Yang 1
Yuliang Wu 1
Bert Geelen 1
Jaehyun Kim 1
Rajeev Rao 1
Dinesh Ramanathan 1
David Van Campenhout 1
Hussain Al-Asaad 1
Rina Panigrahy 1
Jonathan Martin 1
Hao Li 1
Vijay Sundararajan 1
Juan Lanchares 1
Rajiv Gupta 1
Christophe Bobda 1
Tianshi Chen 1
Depei Qian 1
Hungsheng Chang 1
Salvador Mir 1
E Mariatos 1
Yoshiaki Fukui 1
Hsinhung Lin 1
YannRue Lin 1
Yihlang Li 1
Mohamed Zahran 1
Douglas Myers 1
Robert Brayton 1
Jonghee Youn 1
Yuan Yuan 1
Christian Hochberger 1
Alexander Weiss 1
Christian Panten 1
Yoan Lin 1
Unmesh Bordoloi 1
Petru Eles 1
Marcelo Johann 1
Qiuping Yi 1
Zili Shao 1
Dhiraj Pradhan 1
Chaowen Tzeng 1
Kueichung Chang 1
Jihsheng Shen 1
Joachim Anlauf 1
Sami Taktak 1
Jianli Zhuo 1
Xingguang Feng 1
Yiran Chen 1
Jonghee Yoon 1
Ahmed Abousamra 1
Dongwoo Lee 1
Dirk Niggemeyer 1
Pu Liu 1
Bilge Akgul 1
Tsuangwei Chang 1
Hyunggyu Lee 1
Janet Wang 1
Alexandro Baldassin 1
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Taemin Lee 1
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Dongha Jung 1
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I Tseng 1
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Luca Benini 1
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Yang Xu 1
Jaeyeon Won 1
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Duo Li 1
Lei Jiang 1
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Hiroto Yasuura 1
Peng Yang 1
I Tsai 1
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Christakis Lezos 1
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Chulhong Park 1
Qinke Wang 1
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Eddie Hung 1
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Chincheng Kuo 1
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Xiaojian Yang 1
Stefan Obenaus 1
Shigetoshi Nakatake 1
Nima Darav 1
Chelun Hsu 1
Fujiang Lin 1
Sungkwang Lee 1
Hokyoon Lee 1
Florent De Lamotte 1
Seokhyeong Kang 1
Evangelos Eleftheriou 1
Thomas Griffin 1
Bradley Kiddie 1
Daniel Limbrick 1
Xin Huang 1
Ramin Bashizade 1
Youtao Zhang 1
Qingling Zhao 1
Mohammad Azarbad 1
Scott Brandt 1
Martin Streubühr 1
Jens Gladigau 1
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Juan Hamers 1
Joseph Ganley 1
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Chunhan Chen 1
Chinghwa Cheng 1
Yaoguang Wei 1
Cliff Sze 1
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Yokesh Kumar 1
Dimitris Bakalis 1
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Laurence Yang 1
Kan Xiao 1
Fulvio Corno 1
Andy Lambrechts 1
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Xing Hu 1
Shuangchen Li 1
Yining Zhang 1
Thanos Stouraitis 1
MingChing Lu 1
Lipin Chang 1
ChiaoChen Fang 1
Upavan Gupta 1
Venkataraman Mahalingam 1
Bernd Becker 1
Chifeng Li 1
Jeonghun Cho 1
Ritayu Chen 1
Jiliang Zhang 1
Eddie Cheng 1
Christian Buckl 1
Kamel Beznia 1
Hongyu Chen 1
Franz Franchetti 1
Jun Matsushima 1
Shigeki Ohbayashi 1
Pengchih Wang 1
Yumin Kuo 1
Andrew Kennings 1
Duo Liu 1
Érika Cota 1
Marcelo Lubaszewski 1
Nicolas Blanc 1
Rafael Rosales 1
William Song 1
Chen Huang 1
Joonho Kong 1
George Kornaros 1
Richard Lasslop 1
Jens Vygen 1
Qing Wu 1
John Jose 1
M Joseph 1
Yenpo Ho 1
Srijan Kumar 1
Fangming Ye 1
Jaiming Lin 1
Ganapathy Parthasarathy 1
Smita Krishnaswamy 1
A Abbasian 1
Kyungsoo Lee 1
Mengchiou Wu 1
Xi Chen 1
Seher Kiziltepe 1
Guanying Wu 1
Fabrizio Lombardi 1
Bruno Girodias 1
Youcef Bouchebaba 1
Gabriela Nicolescu 1
Swaroop Ghosh 1
QingPing Tan 1
Jinfeng Liu 1
Maurice Bruynooghe 1
Karam Chatha 1
Mukund Narasimhan 1
Naran Sirisantana 1
Alex Yakovlev 1
Yinlong Xu 1
Christoph Kern 1
Zhaoliang Pan 1
Wei Zhao 1
Sreejit Chakravarty 1
Hungyi Li 1
Vladimir Zolotov 1
Stefano Quer 1
Henrik Esbensen 1
Li Shang 1
Zhuo Feng 1
Santiago Rodríguez 1
Maria García 1
Marc Heijligers 1
Weitong Chuang 1
Sagar Sabade 1
Einar Aas 1
Xiaoping Tang 1
Jaehwanjohn Lee 1
Subhankar Mukherjee 1
Pallab Dasgupta 1
Ruijing Shen 1
Diederik Verkest 1
David Kolson 1
Kuochen Wang 1
Jun Chen 1
Hakan Yalcin 1
Franck Yonga 1
Ling Li 1
Yunji Chen 1
Chinchi Teng 1
Chibang Kuan 1
Phillip Jones 1
Ahcène Bounceur 1

Affiliation Paper Counts
Hynix Semiconductor Inc. 1
Lebanese American University 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
Indian Institute of Management Calcutta 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
Macau University of Science and Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
Huawei Technologies Co., Ltd. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
Capital Normal University China 1
University of Twente 1
East China Normal University 1
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Russian Academy of Sciences 1
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Microsoft Research 1
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Royal Military College of Canada 1
Nokia 1
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Oracle Corporation 1
NXP Semiconductors 1
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Siemens AG 1
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Karlsruhe Institute of Technology, Campus South 1
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Institute of Computing Technology Chinese Academy of Sciences 1
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Texas Instruments (India) Ltd 1
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Google Inc. 1
Spanish National Research Council 1
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Thomson, SA 1
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Commissariat a L'Energie Atomique CEA 1
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Samsung Group 1
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Feng Chia University 2
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Altera Corporation 2
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King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
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Japan Advanced Institute of Science and Technology 2
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Infineon Technologies AG 2
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Avant Corporation 2
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Electronics Telecommunication Research Institute 3
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Korea University 3
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TIMA Laboratoire 4
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University College Dublin 4
Motorola Austin 4
Louisiana State University 4
Chung Hua University 4
City University of Hong Kong 4
Peking University 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
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Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
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Microsoft 4
IBM Austin Research Laboratory 4
University of Milan 4
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Universite de Rennes 1 4
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Macronix International Co 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
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Agilent Technologies 5
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Technical University of Madrid 5
IBM Zurich Research Laboratory 5
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Nanjing University 5
Fujitsu America, Inc. 5
New York University Abu Dhabi 5
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University of Illinois 6
Fudan University 6
Indian Institute of Technology, Guwahati 6
Brown University 6
University of California, Davis 6
Holst Centre 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
National Taiwan University of Science and Technology 6
Swiss Federal Institute of Technology, Lausanne 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
Universite Grenoble Alpes 6
Universidade de Lisboa 6
University of Minnesota System 7
Linkoping University 7
HP Labs 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
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Technion - Israel Institute of Technology 7
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University of Freiburg 9
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The University of British Columbia 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
Indian Statistical Institute, Kolkata 10
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Broadcom Corporation 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
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Chung Yuan Christian University 10
NEC Corporation 10
Princeton University 11
Yuan Ze University 11
University of Massachusetts Amherst 11
Imperial College London 11
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Samsung Electronics 12
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University of Waterloo 12
National University of Defense Technology China 12
Korea Advanced Institute of Science & Technology 12
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University of Patras 13
University of South Florida Tampa 14
Academia Sinica Taiwan 14
University of Science and Technology of China 14
Catholic University of Leuven 14
Complutense University of Madrid 14
National Chung Cheng University 15
Hong Kong Polytechnic University 15
University of Tehran 15
University of California, Berkeley 15
Renesas Electronics Corporation 15
Chinese Academy of Sciences 16
University of Arizona 17
University of Erlangen-Nuremberg 18
Cadence Design Systems 18
University of Southern California 18
Ghent University 18
Pennsylvania State University 20
Arizona State University 20
Georgia Institute of Technology 20
Virginia Tech 20
University of Illinois at Urbana-Champaign 21
University of California, Santa Barbara 21
Tsinghua University 24
National Cheng Kung University 25
University of Maryland 26
Eindhoven University of Technology 26
Synopsys Incorporated 28
Chinese University of Hong Kong 30
Duke University 31
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Intel Corporation 33
Polytechnic Institute of Turin 34
University of Texas at Austin 35
University of Pittsburgh 37
Purdue University 40
Carnegie Mellon University 40
National Taiwan University 43
University of California, San Diego 43
National Chiao Tung University Taiwan 44
University of California, Riverside 44
Indian Institute of Technology, Kharagpur 51
Texas A and M University 51
University of California, Irvine 63
University of California, Los Angeles 65
Seoul National University 67
National Tsing Hua University 68

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Volume 22 Issue 2, January 2017  Issue-in-Progress

Volume 22 Issue 1, December 2016
Volume 21 Issue 4, September 2016
Volume 21 Issue 3, July 2016 Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
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