ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles


The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent ACM/IEEE International Symposium on Physical Design (ISPD) contests. In this article, the framework of... (more)

Clock-Tree-Aware Incremental Timing-Driven Placement

The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step toward timing closure.... (more)

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective... (more)

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been... (more)

Differential Write-Conscious Software Design on Phase-Change Memory

Phase-change memory (PCM) has several benefits including low cost, non-volatility, byte-addressability, etc., and limitations such as write endurance.... (more)


With the sharp increase of very large-scale integrated (VLSI) circuit density, we are faced with many knotty issues. Particularly in the routing phase of VLSI physical design, the interconnection effects directly relate to the final performance of circuits. However, the optimization capability of traditional rectilinear architecture is limited;... (more)


Best Paper Award: Congratulations to Chung-Wei Lin, Bowen Zheng, Qi Zhu, and Alberto Sangiovanni-Vincentelli on receiving the 2016 ACM TODAES Best Paper Award for their article titled Security-Aware Design Methodology and Optimization for Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1, Article 18, November 2015.

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

Forthcoming Articles
Statistical Rare Event Analysis and Parameter Guidance by Elite Learning Sample Selection

Accurately estimating the failure region of rare events for memory-cell and analog circuit blocks under process variations is a challenging task. In this article, we propose a new statistical method, called EliteScope to estimate the circuit failure rates in rare event regions and to provide conditions of parameters to achieve targeted performance. The new method is based on the iterative blockage framework to reduce the number of samples. But it consists of two new techniques to improve existing methods. First, the new approach employs an elite learning sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the EliteScope identifies the failure regions in terms of parameter spaces to provide a good design guidance to accomplish the performance target. It applies variance based feature selection to find the dominant parameters and then determine the in-spec boundaries of those parameters.We demonstrate the advantage of our proposed method using several memory and analog circuits with different number of process parameters.Experiments on four circuit examples show that it EliteScope achieves a significant improvement on failure region estimation in terms of accuracy and simulation cost over traditional approaches.The 16-bit 6T-SRAM column example also demonstrate that the new method is scalable for handling large problems with large number of process variables.

EBL Overlapping aware Stencil Planning for MCC System

Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters) can be printed in one shot. Recently the traditional EBL system is extended into multi-column cell (MCC) system to further improve the throughput. In MCC system, several independent CPs are used to further speed-up the writing process. Because of the area constraint of stencil, MCC system needs to be packed/planned carefully to take advantage of the characters. In this paper, we prove that the overlapping aware stencil planning (OSP) problem is NP-hard. Then we propose E-BLOW, a tool to solve MCC system OSP problem. E-BLOW involves several novel speedup techniques, such as successive relaxation and dynamic programming. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system.

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

Hierarchical Statistical Leakage Analysis and Its Application

In this paper, we investigate a hierarchical statistical leakage analysis design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power analysis. To solve the challenges of incorporating spatial correlations between IP modules at system level, we first propose a method to extract correlation-inclusive leakage models. Then a method to handle the spatial correlations at system level is also proposed. Using this method the runtime of system statistical leakage analysis can be significantly improved without disclosing the netlists of the IP modules. Experimental results demonstrate that the proposed hierarchical statistical leakage analysis method is about 100 times faster than the gate-level full-chip statistical leakage analysis methods while the accuracy of statistical leakage analysis is still well maintained. In addition, we also investigate one application of this hierarchical statistical leakage analysis method, a leakage-yield-driven floorplanning framework, to demonstrate the benefits of such hierarchical statistical leakage analysis method in practice. At the same time, we also propose an optimized hierarchical leakage analysis method dedicated for the floorplanning framework. The effectiveness of the floorplanning framework and the optimized method is also confirmed by the experimental results.

PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, e.g., in 14nm and below, where double patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches such as M2 and M3. Self-aligned double patterning (SADP) provides better control on the line edge roughness and overlay but it has very restrictive design constraints and prefers regular layout patterns. This paper presents a comprehensive pin access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include pre-computation of both intra-cell and inter-cell pin accessibility, as well as local and global pin access planning to enable the handshaking between standard cell level pin access and detailed routing under SADP constraints. Pin access driven rip- up and re-route scheme is further proposed to improve the ultimate routability. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

Analytical Clustering Score with Application to Post-Placement Register Clustering

Circuit clustering is usually done through discrete optimizations, with the purpose of circuit size reduction or design-specific cluster formation. Specifically, we are interested in the register clustering technique for clock power reduction. The emerging of multi-bit flip-flop (MBFF) brings new opportunity. INTEGRA was the only existing post-placement MBFF clustering optimizer with a sub-quadratic time complexity. However, it degrades the wirelength severely, especially for realistic designs, which may cancel out the benefits of MBFF clustering. In this paper we enable the formulation of an analytical clustering score in nonlinear programming, where the wirelength objective can be seamlessly integrated and the solver has sub-quadratic time complexity. The application of this analytical method to MBFF clustering reduces the clock power by about 20% as the state-of-the-art techniques, and further reduces the wirelength by about 25%. Even without MBFF library, the application of our analytical method for register clustering can still reduce clock wirelength by about 30%. In addition, the proposed method is promising to be integrated in an in-placement MBFF clustering solver and be applied in other problems which require formulating the clustering score in the objective function.

Hardware Trojans: Lessons Learned After One Decade of Research

Given the increasing complexity of modern electronics and the cost of fabrication, entities from around the globe have become more heavily involved in all phases of the electronics supply chain. In this environment, hardware Trojans (i.e., malicious modifications or inclusions made by untrusted third parties) pose major security concerns, especially for those integrated circuits (ICs) and systems used in critical applications and cyber infrastructure. While hardware Trojans have been explored significantly in academia over the last decade, there remains room for improvement. In this article, we examine the research on hardware Trojans from the last decade and attempt to capture the lessons learned. A comprehensive adversarial model taxonomy is introduced and used to examine the current state-of-the-art. Then the past countermeasures and publication trends are categorized based on adversarial model and topic. Through this analysis, we identify what has been covered and the important problems that are under investigated. We also identify the most critical lessons for those new to the field and suggest a roadmap for future hardware Trojan research.

Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow

The Scenario-Aware Dataflow (SADF) model is based on concurrent actors that interact via channels. It combines streaming data and control to capture scenarios while incorporating hard and soft real-time aspects. To model data-flow computations that are subject to uncertainty, SADF models are equipped with random primitives. We propose to use probabilistic model checking to analyse uncertain SADF models. We show how measures such as expected time, long-run objectives like throughput, as well as timed reachability can a given system configuration be reached within a deadline with high probability?can be automatically determined. The crux of our method is a compositional semantics of SADF with exponential agent execution times combined with automated abstraction techniques akin to partial-order reduction. We present the semantics in detail, and show how it accommodates the incorporation of execution platforms enabling the analysis of energy consumption. The feasibility of our approach is illustrated by analysing several quantitative measures of an MPEG-4 decoder and an industrial face recognition application.

Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore and Memory

With the breakdown of Dennards Scaling over the past decade, performance growth of modern microprocessor design has largely relied on scaling core count in CMPs (Chip Multiprocessors). The challenge of chip power density, however, remains and demands new power management solutions. This work investigates a coordinated CMP system-wide DVFS (Dynamic Voltage and Frequency Scaling) policy centered around shared resource utilization. This approach represents a new angle on the problem, different from the conventional core-workload driven approaches. The key component of our work is per-core DVFS leveraging a technique similar to TCP-Vegas congestion control from networking. This TCP-Vegas-based DVFS can potentially identify the synergy between power reduction and performance improvement. Further, this work includes uncore (on-chip interconnect and shared last level cache) and main memory DVFS policies coordinated with the per-core DVFS policy. Full system simulations on PARSEC benchmarks show that our technique reduces total energy dissipation by over 47% across all benchmarks with less than 2.3% performance degradation. Our work also leads to 12% more energy savings compared to a prior work CMP DVFS policy.

Ensemble Reduction via Logic Minimization

An ensemble of machine learning classifiers usually improves generalization performance and is useful for many applications. However, the extra memory storage and computational cost incurred from the combined models often limits their potential applications. In this paper, we propose a new ensemble reduction method called CANOPY that significantly reduces memory storage and computations. CANOPY uses a technique from logic minimization for digital circuits to select and combine particular classification models from an initial pool in the form of a Boolean function, through which the reduced ensemble performs classification. Experiments on 20 UCI data sets demonstrate that CANOPY either outperforms or is very competitive with the initial ensemble and one state-of-the-art ensemble reduction method in terms of generalization error, and is superior to all existing reduction methods surveyed for identifying the smallest numbers of models in the reduced ensembles.

Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors

It is challenging to manage the thermal behavior of many-core microprocessors while still keep it running at high-performance since control complexity increases as core number increases. In this paper, a novel hierarchical dynamic thermal management method is proposed to overcome this challenge. The new method employs model predictive control (MPC) with task migration and DVFS scheme to ensure smooth control behavior and negligible computing performance sacrifice. In order to be scalable to many-core system, the hierarchical control scheme is designed with two levels. At the lower level, the cores are spatially clustered into blocks, and local task migration is used to match current power distribution with the optimal distribution calculated by MPC. At the upper level, global task migration is used with the unmatched powers from the lower level. A modified iterative minimum cut algorithm is used to assist the task migration decision making if the power number is large at the upper level. Finally, DVFS is applied to regulate the remaining unmatched powers. Experiments show that the new method is highly scalable to many-core microprocessors with little computing performance compromises and outperforms existing methods.

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology node independent design methodology for these rail clamp circuits that takes process, voltage, and temperature variations into consideration. The methodology can be used as a cookbook by the designer or be used to automate the entire design process. Tradeoffs between various design metrics such as esd performance (Human Body Model), leakage, and area are considered. Simplified circuit models for the rail clamp are presented to gain insights into its working and to size the circuit components. A rail clamp for core power domain is designed using the proposed approach in 40 nm low power process and performance results of the design are also presented. The effectiveness of the design methodology is proven by comparing the obtained design with the best design from among 250,000 designs obtained by randomly sampling from the design space.

A Fast and Scalable Multi-dimensional Multiple-choice Knapsack Heuristic

Power, Area, and Performance Optimization of Standard Cell Memory Arrays through Controlled Placement

Standard cell memories (SCMs) are an alternative to foundry provided SRAM macros that can be defined, synthesized and placed and routed as part of the digital design flow, providing design flexibility, energy efficiency, low-voltage operation, and area efficiency for small memories. However, implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array. In this paper, we present a design methodology for optimizing the physical implementation of SCMs, as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, non-congested layout with high utilization, resulting in reduced area, wire-length, and power consumption. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a 28nm FD-SOI technology, and compared with non-controlled SCMs, as well as with SRAM macros. The controlled SCMs provide an average 25% reduction in area, as compared to non-controlled implementations. Power and performance comparisons of controlled SCM blocks of a commonly found 256X32 (1kbyte) memory with foundry provided SRAMs show over 65% and 10% reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC based test-chip, providing more than 50% power reduction, as compared to equivalently sized compiled SRAMs under a benchmark application.

Accurate Modeling of Nonideal Low Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit Averaging Techniques

The development of enhanced modeling techniques for the simulation of switched-mode Pulse Width Modulated (PWM) DC-DC power converters using circuit averaging is the main focus of this paper. The circuit averaging technique has traditionally been used to model the behavior of PWM DC-DC converters without considering important nonideal characteristics of the switching devices. As a result, most of these existing approaches present simplified models that are ideal or linearized, and do not accurately account for the performance characteristics of the converter. This is especially problematic for low-power applications. In this paper, we present an enhanced nonideal behavioral circuit averaged model that makes the simulation of DC-DC converters both computationally efficient and accurate, thereby presenting an important tool for circuit designers. Experimentally, we show that our Verilog-A based new model allows for accurate simulation of both Buck and Boost type PWM converters operating in either CCM or DCM modes while providing more than one order of magnitude speedup over the transistor-level simulation.

Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs

This paper introduces a Cyber-physical Co-Simulation Framework (CPCSF) for design and analysis of smart cells that enable scalable battery pack and Battery Management System (BMS) architectures. In contrast to conventional cells in battery packs, where all cells are monitored and controlled centrally, each smart cell is equipped with its own electronics in the form of a Cell Management Unit (CMU). The CMU maintains the cell in a safe and healthy operating state, while system-level battery management functions are performed by cooperation of the smart cells via communication. Here, the smart cells collaborate in a self-organizing fashion without a central controller instance. This enables maximum scalability and modularity, significantly simplifying integration of battery packs. However, for this emerging architecture, system-level design methodologies and tools have not been investigated yet. Consequently, the systematic design of the hardware/software architecture of smart cells requires a cyber-physical co-simulation of the network of smart cells which has to include all the components from the software, electronic, electric and electrochemical domains. This comprises distributed BMS algorithms running on the CMUs, the communication network, control circuitry, cell balancing hardware and battery cell behavior. For this purpose, we introduce a CPCSF which enables rapid design and analysis of smart cell hardware/software architectures. Our framework is then applied to investigate request-driven active cell balancing strategies that make use of the decentralized system architecture. In an exhaustive analysis on a realistic 21.6kWh Electric Vehicle (EV) battery pack containing 96 smart cells in series, the CPCSF is able to simulate hundreds of balancing runs together with all system characteristics, using the proposed request-driven balancing strategies at highest accuracy within an overall time frame of several hours. Consequently, the presented CPCSF for the first time allows to quantitatively and qualitatively analyze the behavior of smart cell architectures for real-world applications.

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment based on an Accurate Analytical Statistical Yield-Gradient

In this paper, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (a) discrete gate sizing and (b) simultaneous gate sizing and threshold voltage (VT) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the run-time as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and VT assignment. We also propose heuristics for resizing/changing the VT of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC'99 benchmarks show that the proposed multi-node resizing algorithm results in a significant improvement in the run-time with a marginal average area penalty and no cost to the final yield achieved.

Performance Evaluation of NoC-based Multicore Systems: From Traffic Analysis to NoC Latency Modelling

In this survey, we review several mathematical approaches for performance evaluation of NoC-based multicore systems, starting from the traffic analysis to the complex NoC models for latency evaluation. Towards this end, we first summarize the NoC workload to capture the application traffic characteristics. Specifically, we focus on techniques of non-Poisson and fractal (i.e., self-similar or long range memory dependent) traffic models and their impacts on the multicore platform design. Then, we review the analytical techniques for evaluating the performance of an NoC under the given input traffic. We investigate NoC analytical models for average as well as maximum latency predictions. Another interesting research direction in NoC performance evaluation consists of combining simulation and analytical models in order to exploit their advantages together. Towards this end, we discuss several newly proposed approaches that use hardware-based or learning-based techniques.

N-Detection Test Sets for Circuits with Multiple Independent Scan Chains

In a circuit with multiple independent scan chains, it is possible to operate groups of scan chains independently in functional or shift mode. This design-for-testability approach can be used for increasing the quality of a test set. This paper describes an N-detection test generation procedure for increasing the quality of a transition fault test set in such a circuit. The procedure uses the possibility of applying the same test, with the scan chains operating in different modes, to increase the numbers of detections without increasing the number of tests that need to be generated or stored on a tester. This results in reduced input storage requirements compared with a conventional N-detection test set, and an increased number of applied tests. The increased quality of the test set is verified by its bridging fault coverage.

Periodic Scan-in States to Reduce the Input Test Data Volume for Partially-Functional Broadside Tests

This paper describes a procedure for test data compression targeting functional and partially-functional broadside tests. The scan-in state of such a test is either a reachable state or has a known Hamming distance from a reachable state. Reachable states are fully-specified, while the popular LFSR-based test data compression methods require the use of incompletely-specified test cubes. The test data compression approach considered in this paper is based on the use of periodic scan-in states. Such states require the storage of a period that can be significantly shorter than a scan-in state, thus providing test data compression. The procedure computes a set of periods that is sufficient for detecting all the detectable target faults. Considering the scan-in states that the periods produce, the procedure ranks the periods based on the distances of the scan-in states from reachable states, and the lengths of the periods. Functional and partially-functional broadside tests are generated preferring shorter periods with smaller Hamming distances. The results are compared with those of an LFSR-based approach.

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip

Digital (droplet-based) microfluidic technology offers an attractive platform for implementing a wide variety of biochemical laboratory protocols, such as point-of-care diagnosis, DNA analysis, target detection, and drug discovery. However, because of the inherent uncertainty of fluidic operations, the outcome of biochemical experiments performed on-chip can be erroneous even if the chip is tested a priori and deemed to be defect-free. In this paper, we address an important error-recoverability problem in the context of sample preparation. We assume a cyberphysical environment, in which the physical errors, when detected online at selected checkpoints with integrated sensors, can be corrected through recovery techniques. However, almost all prior work on error recoverability used a checkpointing-based rollback approach, i.e., re-execution of certain portion of the protocol starting from the previous checkpoint. Unfortunately, such techniques are expensive both in terms of assay-completion time and reagent cost, and can never ensure full error-recovery in a deterministic sense. We consider imprecise droplet mix-split operations and present a novel roll-forward approach where the erroneous droplets, thus produced, are used in the error-recovery process, instead of being discarded or re-mixed. All erroneous droplets participate in the dilution process and they mutually cancel or reduce the concentration error when the target droplet is reached.We also present a rigorous analysis that discovers the role of volumetric error on the concentration of a sample to be prepared, and we describe the layout of a lab-on-chip that can execute the proposed cyberphysical dilution algorithm. Our analysis reveals that fluidic errors caused by unbalanced droplet splitting can be classified as being either critical or non-critical, and only those of the former type require correction to achieve error-free sample dilution. Simulation experiments on various sample preparation test cases demonstrate the effectiveness of the proposed method.

Efficient Security Monitoring with Core Debug Interface in an Embedded Processor

Many researchers have proposed the concept of security monitoring, which watches the execution behavior of a program (e.g, control-flow or data-flow) running on the machine to find the existence of attacks. Among the proposed approaches in the literature, software-based works are known to be relatively easy to be adopted to the commercial products, but may incur tremendous runtime overhead. Although many hardware-based solutions provide high performance, the inherent problem of them is that they usually mandate drastic change to the internal processor architecture. More recent ones to minimize the change have proposed external devices for security monitoring. However, these approaches intrinsically suffer from the high overhead to communicate with their external devices. Consequently, they either significantly lose performance, or inevitably make invasive modifications to the processor inside. Our solution also relies on external hardware for security monitoring, but unlike theirs, ours exploits the core debug interface (CDI) to tackle the communication issue. CDI is readily available in most commercial processors for debugging so that we can build our system simply by plugging our hardware to the processor via CDI, precluding the need for altering the processor itself. To validate the effectiveness of our approach, we implement two well-known monitoring techniques on our proposed framework; dynamic information flow tracking and branch regulation. The empirical results on our FPGA prototype show that our external hardware engines efficiently perform the monitoring schemes mainly thanks to the support of CDI that helps us cut substantially down the communication costs.

On Battery Recovery Effect in Wireless Sensor Nodes

With the perennial demand for longer runtime of battery-powered Wireless Sensor Nodes (WSNs), several techniques have been proposed to increase the battery runtime. One such class of techniques exploiting the battery recovery effect phenomenon claims that performing an intermittent discharge instead of a continuous discharge will increase the usable battery capacity. Several works in the areas of embedded systems and wireless sensor networks have assumed the existence of this recovery effect and proposed different power management techniques in the form of power supply architectures (multiple battery setup) and communication protocols (burst mode transmission) in order to exploit it. However, until now, a systematic experimental evaluation of the recovery effect has not been performed with real battery cells, using high accuracy battery testers to confirm the existence of this recovery phenomenon. In this paper, a systematic evaluation procedure is developed to verify the existence of this battery recovery effect. Our experimental results do not show any evidence of this recovery effect, and in particular, our results show a significant deviation from the stochastic battery models which were used by many power management techniques. Therefore, the existing power management approaches that rely on this recovery effect do not hold in practice. Instead of a battery recovery effect, our experimental results show the existence of the rate capacity effect, which is the reduction of usable battery capacity with higher discharge power, to be the dominant electrochemical phenomenon that should be considered for maximizing the runtime of WSN applications. We outline power management techniques that minimize the rate capacity effect in order to obtain a higher energy output from the battery.

A Survey Of Techniques for Cache Locking

Cache memory, although important for boosting application performance, is also a source of execution time variability, which makes its use difficult in systems requiring WCET (worst case execution time) guarantees. Cache locking (CL) is a promising approach for simplifying WCET estimation and providing predictability and hence, several commercial processors provide ability for locking cache. However, CL also has its disadvantages (e.g. extra misses for unlocked blocks, complex algorithms required for selection of locking contents) and hence, a careful management is required to realize the full potential of CL. In this paper, we present a survey of techniques proposed for cache locking. We categorize the techniques in several groups to underscore their similarities and differences. We also discuss the opportunities and obstacles in using CL. We hope that this paper will help researchers in getting insights into CL schemes and will also stimulate further work in this area.

Streaming Sorting Networks

Library-based Placement and Routing in FPGAs with Support of Partial Reconfiguration

While traditional FPGA design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used module can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this paper, we propose a library-based placement and routing flow, which best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 77% on average with up to 20% area overhead compared with fine-grained results of VPR through the reuse of module information in the library. Our proposed tool also achieves 4% to 21% improvement in delay in comparison with VPR.

An Effective Chemical Mechanical Polishing Fill Insertion Approach

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This paper presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approachesFast Median approach , LP approach and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

Timing Path Driven Cycle Cutting for Sequential Controllers

Power and performance optimization of integrated circuits is performed by timing driven algorithms that operate on directed acyclic graphs. Sequential circuits and circuits with topological feedback contain cycles. Cyclic circuits must be represented as directed acyclic graphs to be optimized and evaluated using static timing analysis. Algorithms in commercial electronic design automation tools generate the required acyclic graphs by cutting cycles without considering timing paths. This work reports on a method for generating directed acyclic circuit graphs which do not cut the specified timing paths. The algorithm is applied to over 125 benchmark designs and asynchronous handshake controllers. The runtime is less than one second, even for even the largest published controllers. Circuit timing graphs generated using this method retain the necessary timing paths which enables circuit validation and optimization employing the commercial tools. Additional benefits show these designs are on an average a third in size, operate 33.3% faster, and consume one fourth the energy.

Synthesis of Dual-Mode Circuits through Library Design, Gate Sizing, and Clock Tree Optimization

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to minimize performance loss at NTV or maximize NTV-mode frequency. A standard cell library for dual-mode circuits is proposed; we balance transistor sizes and reduce stack transistors. Gate sizing is performed to minimize negative slacks at both modes; a new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV-mode frequency. Clock tree synthesis is re-formulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV-mode clock period is reduced by 24% on average; clock skew at NTV decreases by 13% on average.

Path Selection for Real-Time Communication on Priority-Aware NoCs

This work investigates selecting paths for communication flows when deploying a hard real-time application on a chip-multiprocessor system. This chip-multiprocessor system uses a priority-aware real-time network-on-chip interconnect between the processors. Given a mapping of the computation tasks onto the chip-multiprocessor, the problem we address in this work is to discover paths the communication flows take such that hard real-time deadlines of flows are met. Furthermore, we must ensure that deadlines are met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a stage-level analysis for real-time communication to determine the impact of a network link being used by a flow, and its effect on other flows sharing the link. The path selection algorithm uses heuristics such as selecting links with least interference, and considering lower priority flows when dedicating links to paths of higher priority flows since an optimal one is intractable. The algorithm also considers constraints on the number of virtual channels at each router port in the network. The statistically significant experimental results show an improvement in schedulability by 5% and 12% over existing path selection algorithms such as Minimum Interference Routing and Widest Shortest Path algorithms, respectively. We also present a set-top box case study to further illustrate the benefits of using the proposed algorithm.

Area-aware Decomposition for Single-Electron Transistor Arrays

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moores law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large reconfigurable SET array where the height of SET array equals the number of primary inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say 10, rather than arbitrary value due to the ultra-low driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large SET array into a set of small SET arrays where each of them realizes a subfunction of the original circuit with no more than 10 inputs. Thus, this paper presents two techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced. The width minimization algorithm leads to a 25%~41% improvement compared to the state-of-the-art, and the mapping algorithm achieves a 60% reduction in total area compared to a nai1ve approach.

Improving PCM Endurance with a Constant-cost Wear Leveling Design

Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling is an effective way to improve PCM endurance, but its major challenge is how to efficiently determine the appropriate memory pages for allocation or swapping. In this paper, we present a constant-cost wear leveling design that is compatible with existing memory management. Two implementations, namely bucket-based and array-based wear leveling, with constant-time (or nearly zero) search cost are proposed to be integrated into the OS layer and the hardware layer respectively, as well as to trade between time and space complexity. The results of experiments conducted based on an implementation in Android, as well as simulations with popular benchmarks, to evaluate the effectiveness of the proposed design are very encouraging.

Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization

As finite energy resources are being consumed at faster rate than they can be replaced, renewable energy resources have drawn an extensive attention. Wind power development is one such example growing significantly throughout the world. The main difficulty in wind power development is that wind turbines interfere with each other. The produced turbulence, wake effect, directly reduces the power generation. In addition, wirelength of collection network among wind turbines is not merely an economic factor, but also it decides power loss in the wind farm. Moreover, in reality, obstacles (e.g., building, lake, etc.) exist in the wind farm which are unavoidable. Nevertheless, to the best of our knowledge, none of the existing works consider wake effect, wirelength and obstacle-avoiding all together in the wind turbine placement problem. In this paper, we propose an analytical method to obtain the obstacle-avoiding placement of wind turbines minimizing both power loss and wake effect. We also propose a post-processing method to fine-tune the solution obtained from the analytical method to find better solution. Simulation results show that our tool is 12x faster than the state-of-the-art industrial tool AWS OpenWind and 203x faster than the state-of-the-art academic tool TDA with almost the same produced power.

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement

Routability is one of the most important problems in high performance circuit designs. From the viewpoint of placement design, two major factors cause routing congestion: 1) interconnections between cells, and 2) connections on macro blockages. In this paper, we present a routability-driven placer Ripple 2.0 which emphasizes both kinds of routing congestion. Several techniques will be presented, including 1) cell inflation with routing path consideration, 2) congested cluster optimization, 3) routability-driven cell spreading, and 4) simultaneous routing and placement for routability refinement. With the official evaluation protocol, Ripple 2.0 outperforms other published academic routability-driven placers. Compared with top results in ICCAD 2012 contest, Ripple 2.0 achieves better detailed routing solution obtained by a commercial router.

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs

With the advent of globalization in the semiconductor industry, it is necessary to prevent unauthorized usage of third party IPs (3PIPs), cloning and unwanted modification of 3PIPs, and unauthorized production of ICs. Due to the increasing complexity of ICs, system-on-chip (SoC) designers use various 3PIPs in their design to reduce time-to-market and development costs, which creates a trust issue between the SoC designer and the IP owners. In addition, as the ICs are fabricated around the globe, the SoC designers give fabrication contracts to offshore foundries to manufacture ICs and have little control over the fabrication process, including the total number of chips fabricated. Similarly, the 3PIP owners lack control over the number of fabricated chips and/or the usage of their IPs in an SoC. In this paper, we present a comprehensive solution for preventing IP piracy and IC overproduction by assuring forward trust between all entities involved in the SoC design and fabrication process. We propose a novel design flow to prevent IC overproduction and IP overuse. We have used asymmetric and symmetric key encryption, in a fashion similar to Pretty Good Privacy (PGP), to transfer keys from the SoC designer or 3PIP owners to the chips. In addition, we also propose to attach an IP digest (a cryptographic hash of the entire IP) to the header of an IP to prevent modification of the IP by the SoC designers. We have shown that our approach is resistant to various attacks with the cost of minimal area overhead.

Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling

Multicore platforms are increasingly used in real-time embedded applications. In the development of such applications, an efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and allowing savings in stack space. In this paper, we address the problem of mapping tasks to cores and assignment of the scheduling parameters for both partitioned Fixed-Priority and EDF scheduling algorithms with PTS. We formulate the optimization problems using Mixed Integer Linear Programming framework, and present a Simulated Annealing algorithm as well as an efficient heuristic algorithm as practical alternatives. We perform extensive performance evaluations using random synthetic tasksets and industrial case studies.

Hybrid Power Management for Office Equipment

Office machines (such as printers, scanners, fax, and copiers) can consume significant amounts of power. Most office machines have sleep modes to save power. Power management of these machines are usually timeout-based: a machine sleeps after being idle long enough. Setting the timeout duration can be difficult: if it is too long, the machine wastes power during idleness. If it is too short, the machine sleeps too soon and too often the wakeup delay can significantly degrade productivity. Thus, power management is a tradeoff between saving energy and keeping response time short. Many power management policies have been published and one policy may outperform another in some scenarios. There is no definite conclusion which policy is always better. This paper describes two methods for office equipment power management. The first method adaptively reduces power based on a constraint of the wakeup delay. The second method is a hybrid method with multiple candidate policies and it selects the most appropriate power management policy. Using six months of request traces from 18 different printers, we demonstrate that the hybrid policy outperforms individual policies. We also discover that power management based on business hours does not produce consistent energy savings.

A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition using Wearables (post conference paper)

Wearables are being widely utilized in health and wellness applications, primarily due to the recent advances in the sensor and wireless communication, which enhance the promise of wearable systems in providing continuous and real-time monitoring and interventions. Wearables are generally composed of hardware/software components for collection, processing, and communication of physiological data. Practical implementation of wearable monitoring in real-life applications is currently limited due to notable obstacles. The wearability and form factor are dominated by the amount of energy needed for sensing, processing and communication. In this paper, we propose an ultra low-power granular decision making architecture, also called screening classifier, which can be viewed as a tiered wake up circuitry, consuming three orders of magnitude less power than the state-of-the-art low-power microcontrollers. This processing model operates based on computationally simple template matching modules, which is ideally performed with low sensitivity but operates at low power. Initial template matching rejects signals that are clearly not of interest from the signal processing chain keeping the rest of processing blocks idle. If the signal is likely of interest, the sensitivity and the power of the template matching modules are gradually increased and ultimately the main processing unit is activated. We pose optimization techniques to efficiently split a full template into smaller bins, called mini-templates, and activate only a subset of bins during each classification decision. Our experimental results on real data show that this signal screening model reduces power consumption of the processing architecture by a factor of 70% while the sensitivity of detection remains at least 80%.

Construction of Reconfigurable Clock Trees for MCMM Designs using Mode Separation and Scenario Compression

The clock networks of many modern circuits have to operate in multiple corners and multiple modes (MCMM). We propose to construct mode-reconfigurable clock trees (MRCTs) based on mode separation and scenario compression. The technique of scenario compression is proposed to consider the timing constraints in multiple scenarios at the same time, compressing the MCMM problem into an equivalent single-corner multiple-mode (SCMM), or single-corner single-mode (SCSM) problem. The compression is performed by combining the skew constraints of the different scenarios in skew constraint graphs based on delay linearization and dominating skew constraints. An MRCT consists of several clock trees and mode separation involves, depending on the active mode, selecting one of the clock trees to deliver the clock signal. To limit the overhead, the bottom part (closer to the clock sinks) of all the different clock trees are shared and only the top part (closer to the clock source) of the clock network is mode reconfigurable. The reconfigurable is realized using OR-gates and an one-input-multiple-output demultiplexer. The experimental results show that for a set of synthesized MCMM circuits, with 715 to 13, 216 sequential elements, the proposed approach can achieve high yield.

Preface to Special Section on New Physical Design Techniques for the Next Generation Integration Technology

A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture

Multicore processors have proliferated several domains ranging from small scale embedded systems to large datacenters, making tiled CMPs (TCMP) the essential next generation scalable architecture. NUCA archi-tectures help in managing the capacity and access time for such larger cache designs. It divides the last level cache (LLC) into multiple banks connected through on chip network. Static NUCA (SNUCA) has a fixed ad-dress mapping policy whereas dynamic NUCA (DNUCA) allows blocks to relocate nearer to the processing cores at runtime. To allow this DNUCA divides the banks into multiple banksets and a block can be placed in any bank within a particular bankset. The entire bankset may need to be searched to access a block. Optimal bankset searching mechanisms are essential for getting the benefits from DNUCA. This paper proposes a DNUCA based TCMP architecture called TLD-NUCA. It reduces the LLC access time of TCMP and also allows a heavily loaded bank to distribute its load among the underused banks. Instead of other DNUCA designs TLD-NUCA considers only one bankset, hence a block can be placed in any bank. Such relaxations results in more uniform load distribution than existing DNUCA based TCMP (T-DNUCA). Considering single bankset improves the utilisation factor but T-DNUCA cannot implement it because of its expensive searching mechanism. TLD-NUCA uses a centralised directory, called TLD, to search a block from all the banks. Experimental analysis found that TLD-NUCA improves performance by 6% as compared to T-DNUCA. The improvement is 12% as compared to the SNUCA based TCMP design.

State assignment and optimization of ultra high speed FSMs utilizing tri-state buffers

The logic synthesis of ultra high speed FSMs is presented. The state assignment is based on a well known method that uses output vectors. This technique is adjusted to include elements of two-level minimization and takes into account the limited number of terms contained in the logic cell. The state assignment is based on a special form of the binary decision tree. The second phase of the FSM design is logic optimization. The optimization method is based on tri-state buffers, thus making possible a one-logic-level FSM structure. The key point is to search partition variables that control the tri-state buffers. This technique can also be applied to combinational circuits or the output block of FSMs only. Algorithms for state assignment and optimization are presented and richly illustrated by examples. The method is dedicated to using specific features of complex programmable logic devices. Experimental results prove its effectiveness. The optimization method using tri-state buffers and a state assignment binary decision tree can be directly applied to FPGA-dedicated logic synthesis.

Critical-Path-Aware High-Level Synthesis with Distributed Controller for Fast Timing Closure

Floorplanning and Topology Synthesis for Application Specific Network-on-Chips with RF-Interconnect

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on chip communication becomes more and more complex and the power consumption imposes the major challenge for designing ASNoCs. In this paper, we first time propose a four-stage floorplanning and topology synthesis approach for ASNoCs with Radio Frequency Interconnect (RF-I). Firstly, considering the advantage of RF-I in long distance on-chip communication, we integrate the floorplanning and clustering to explore the optimal clustering of cores, where the cores belonging to the same cluster will share the same switch for communications, form an island, and occupy a contiguous physical region. After the switches and network interfaces are inserted into the floorplan, the allocation of routing paths and the RF-I logical channels are integrated in an iterative procedure to generate fine-grain dynamically reconfigurable ASNoC topologies. Finally, considering the signal integrity of RF-I, we adjust the placement of the switches by a simulated annealing-based method to reduce the number of the RF-I routing corners. To evaluate the placement of switches, we propose a dynamical programming based method to route the transmission line and count the routing corners in linear time. The results show that, using RF-I, we can reduce the power consumption of ASNoCs by 20%-29%.

DC Characteristics and Variability on 90nm CMOS Transistor Array-style Analog Layout

In MOS analog layout, the variability suppression is becoming a major issue as well as the layout efficiency. Introducing a transistor array(TA)-style to analog layout, this paper addresses the layout-dependent variability based on the measurement results of test chips on 90nmCMOS process. In TA-style, a large transistor is decomposed into a set of unified sub-transistors are connected in series or parallel. Focusing one row layout of diffusion-sharing for the multiple gates, we analyze the current direction dependent variability and the leakage current via off-gates for the electrical isolation. Furthermore, we present several analog design cases on TA including analysis of the impact on the DC characteristics caused by the transistor channel decomposition.

Index-Resilient Zero-Suppressed BDDs: Definition and Operations

Zero-Suppressed Binary Decision Diagrams (ZDDs) are widely used data structures for representing and handling combination sets and Boolean functions. In particular, ZDDs are commonly used in CAD for the synthesis and verification of integrated circuits. The purpose of this paper is to design an error resilient version of this data structure, i.e., a self-repairing ZDD. More precisely, we design a new ZDD canonical form, called index-resilient reduced ZDD, such that a faulty index can be reconstruct in time $O(k)$, where $k$ is the number of nodes with a corrupted index. Moreover, we propose new versions of the standard algorithms for ZDD manipulation and construction, which are error resilient during their execution and produce an index-resilient reduced ZDD as output. The experimental results validate the proposed approach.


Publication Years 1996-2016
Publication Count 830
Citation Count 3949
Available for Download 830
Downloads (6 weeks) 2340
Downloads (12 Months) 21424
Downloads (cumulative) 625950
Average downloads per article 754
Average citations per article 5
First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Distinguished Member (2008)
ACM Senior Member (2006)
Nikil D. Dutt ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
Soheil Ghiasi ACM Senior Member (2015)
Matthew Guthaus ACM Senior Member (2013)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
John Lee ACM Senior Member (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Ian Parberry ACM Distinguished Member (2015)
Massoud Pedram ACM Distinguished Member (2008)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
Robert Schreiber ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 17
Nikil Dutt 15
Irith Pomeranz 12
Krishnendu Chakrabarty 12
Jason Cong 12
Tingting Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
Lei He 8
Sheldon Tan 8
Yaowen Chang 8
Frank Vahid 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Spyros Tragoudas 6
Alexandru Nicolau 6
Martin Wong 6
Taewhan Kim 6
Yunheung Paek 6
John Hayes 6
Ryan Kastner 6
Massoud Pedram 6
Igor Markov 6
Radu Marculescu 6
Sudhakar Reddy 6
Ali Dasdan 5
Sharad Malik 5
Jenqkuen Lee 5
Mahmut Kandemir 5
Umit Ogras 5
Kiyoung Choi 5
Bhargab Bhattacharya 5
Kaushik Roy 5
Aviral Shrivastava 5
Rajeev Kumar 5
Giovanni De Micheli 5
Tony Givargis 5
Nagarajan Ranganathan 5
Andrew Kahng 5
Chengkok Koh 5
Roman Lysecky 5
Chungkuan Cheng 5
Jingyang Jou 4
Sunil Khatri 4
Kwangting Cheng 4
Rajesh Gupta 4
Zijiang Yang 4
El Aboulhamid 4
Evangeline Young 4
Aarti Gupta 4
Sule Ozev 4
Xiaobosharon Hu 4
Pinghung Yuh 4
Peter Petrov 4
Shihhsu Huang 4
Hungming Chen 4
Alex Jones 4
Sunyuan Hsieh 4
Hans Wunderlich 4
Naehyuck Chang 4
Jintai Yan 4
Chang Liu 4
Allen Wu 4
Miodrag Potkonjak 4
Preeti Panda 4
Jongeun Lee 4
Dinesh Mehta 4
Hai Zhou 4
Franco Fummi 4
Paulo Flores 4
Dirk Stroobandt 4
Pedro Reviriego 3
Daniel Gajski 3
Madhu Mutyam 3
David Atienza 3
Janak Patel 3
Per Kjeldsberg 3
José Monteiro 3
Chialin Yang 3
Ankur Srivastava 3
Yiping You 3
Chiuwing Sham 3
Nicholas Zamora 3
Enrico Macii 3
Dong Xiang 3
Yinhe Han 3
Edwin Sha 3
Baris Taskin 3
Saojie Chen 3
Elizabeth Rudnick 3
Shuvra Bhattacharyya 3
Hai Wang 3
Priyank Kalla 3
Seda Memik 3
George Constantinides 3
Iris Jiang 3
Waikei Mak 3
Xiaoyu Song 3
Janet Roveda 3
Paul Gratz 3
Yunsi Fei 3
Shiyu Huang 3
Chenjie Yu 3
Arnout Vandecappelle 3
Costas Goutis 3
Peter Cheung 3
Karem Sakallah 3
Shihchieh Chang 3
Twan Basten 3
David Pan 3
Hao Yu 3
Xianlong Hong 3
Greg Stitt 3
Peng Li 3
Chakkuen Wong 3
Krishnendu Chakrabarty 3
Li Wang 3
Dimitrios Kagaris 3
Diana Marculescu 3
Henk Corporaal 3
Praveen Raghavan 3
Karel Bruneel 3
Soonhoi Ha 3
Ramesh Karri 3
Valeria Bertacco 3
Yuan Xie 3
Yuanhao Chang 3
Viktor Prasanna 3
Paolo Prinetto 3
Paoann Hsiung 3
Sreejit Chakravarty 3
Axel Jantsch 3
Wen Jone 3
Guangming Wu 3
Ozcan Ozturk 3
Sisira Panda 3
Zoran Salcic 3
Dipankar Das 3
Masanori Kurimoto 3
Guy Gogniat 3
Yuchin Hsu 3
Chungwen Huang 3
Azadeh Davoodi 3
Fadi Kurdahi 3
Sarma Vrudhula 3
Gianpiero Cabodi 3
Massimo Poncino 3
Pai Chou 3
Juan Maestro 3
Mehdi Tahoori 3
Tsungyi Ho 3
Partha Roop 3
Alberto Sangiovanni-Vincentelli 3
Seongnam Kwon 3
Soheil Ghiasi 3
Kurt Keutzer 3
Thambipillai Srikanthan 3
Majid Sarrafzadeh 3
Xiangrong Zhou 3
Martin Palkovič 3
Yowtyng Nieh 3
Jin Sun 2
Jun Zeng 2
Teiwei Kuo 2
Timothy Sherwood 2
Marc Boulé 2
Guangyu Chen 2
Siddharth Garg 2
Arnab Roy 2
Shihhao Hung 2
Wayne Wolf 2
Steven Wilton 2
Graziano Pravadelli 2
John Gough 2
Avinash Malik 2
Jörg Henkel 2
Swarup Bhunia 2
Susmita Sur-Kolay 2
Paul Thadikaran 2
Ricardo Reis 2
Yiyu Shi 2
Chienchih Huang 2
Chinlong Wey 2
Jwu Chen 2
Younlong Lin 2
C Shi 2
Puneet Gupta 2
Laungterng Wang 2
Jiping Liu 2
Aiqun Cao 2
Roberto Passerone 2
Luciano Lavagno 2
Tajana Rosing 2
Zonghua Gu 2
Eduard Cerny 2
Jun Gu 2
Chandra Suresh 2
Sungjoo Yoo 2
Sunggu Lee 2
Vasilios Kelefouras 2
Poyuan Chen 2
Junji Sakai 2
Abhijit Jas 2
Sungmo Kang 2
Junjuan Xu 2
Melvin Breuer 2
Kai Zhu 2
ChengHsing Yang 2
Manfred Glesner 2
Adnan Aziz 2
Nur Touba 2
Ranga Vemuri 2
Shantanu Dutt 2
Michael Riepe 2
Mohammad Tehranipoor 2
Luiz Dos Santos 2
Magdy Abadir 2
Hongbing Fan 2
Jim Holt 2
Hyesoon Kim 2
Miguel Miranda 2
Matthew Guthaus 2
Gustavo Wilke 2
Doosan Cho 2
Jingyang Jou 2
Vinícius Livramento 2
Muhammet Ozdal 2
Ali Afzali-kusha 2
Avinoam Kolodny 2
Ansuman Banerjee 2
Marlin Mickle 2
Vivek Sarin 2
Hiroaki Inoue 2
Kanupriya Gulati 2
Luís Silveira 2
Yiyu Liu 2
José Mendías 2
Ronald Graham 2
Prabhat Mishra 2
Deming Chen 2
M Balakrishnan 2
Stan Liao 2
Erik Marinissen 2
Mike Lee 2
B Rau 2
Meeta Srivastav 2
Sreeranga Rajan 2
Michael Kochte 2
Bart Mesman 2
Mary Irwin 2
Anna Bernasconi 2
Xin Yuan 2
Bin Liu 2
Francesco Poletti 2
Julien Schmaltz 2
Qing Duan 2
James Cain 2
Leonid Mats 2
Marco Bekooij 2
Franjo Ivančić 2
Kiwook Kim 2
Maurizio Rebaudengo 2
Russell Tessier 2
Kyumyung Choi 2
Robert Walker 2
Janming Ho 2
Sujit Dey 2
Vigyan Singhal 2
Srinivas Devadas 2
Ismail Kadayif 2
Deepak Mathaikutty 2
Levent Aksoy 2
Srinivas Katkoori 2
Maria Michael 2
Smita Bakshi 2
Siddhartha Mukhopadhyay 2
Qinru Qiu 2
Mohammad Arjomand 2
Bo Zhao 2
Rudy Lauwereins 2
Andreas Dandalis 2
Yi Wang 2
Sudhakar Yalamanchili 2
Jagannathan Ramanujam 2
Natarajan Viswanathan 2
Román Hermida 2
Christophe Wolinski 2
Alper Sen 2
Yongjoo Kim 2
Wim Heirman 2
Dimitrios Soudris 2
Zebo Peng 2
Chiachun Tsai 2
Erik Brockmeyer 2
Inki Hong 2
Duncan Walker 2
Sanghamitra Roy 2
Gary Dispoto 2
Jun Yang 2
Farinaz Koushanfar 2
Masahiro Fujita 2
Naiwen Chang 2
Sivaram Gopalakrishnan 2
Yuliang Wu 2
Chrystian Guth 2
Chingren Lee 2
Hafizur Rahaman 2
Joann Paul 2
Sergio Nocco 2
Konstantin Moiseev 2
Swapna Dontharaju 2
Kees Goossens 2
Chinhsien Wu 2
Chao Wang 2
Angeliki Kritikakou 2
Meikang Qiu 2
Masato Edahiro 2
Shmuel Wimer 2
Shenchih Tung 2
Dawei Chang 2
Mario López 2
Arcot Sowmya 2
Rajdeep Mukhopadhyay 2
Peichen Pan 2
Chung Tsao 2
Murali Jayapala 2
Javed Absar 2
Youngsoo Shin 2
Lei Li 2
Krzysztof Kuchcinski 2
Yvon Savaria 2
Sandeep Shukla 2
Kaihui Chang 2
Peiwen Luo 2
Peng Li 2
Rafal Baranowski 2
Valentina Ciriani 2
Pochun Huang 2
Bocheng Lai 2
José Güntzel 2
Elaheh Bozorgzadeh 2
Mehrdad Nourani 2
Chunjason Xue 2
Saraju Mohanty 2
Željko Žilić 2
Xiaoping Hu 2
Marco Murciano 2
Stefano Quer 2
Michel Auguin 2
Michael Hsiao 2
Min Xu 2
Luigi Carro 2
Chiajui Hsu 2
José Pino 2
Jun Yang 2
Xuexin Liu 2
Anmol Mathur 2
Freek Verbeek 2
Zhiyu Zeng 2
Koushik Chakraborty 2
Dongsheng Ma 2
Jochen Jess 2
Akash Kumar 2
Leyla Nazhandali 2
Nicola Bombieri 2
Hui Liu 2
Guihai Yan 2
Zili Shao 2
Jürgen Teich 2
Jos Huisken 2
Chiaming Chang 2
Donald Thomas 2
Hsinhung Chen 2
Ronald Blanton 2
Ozgur Sinanoglu 2
S Ramesh 2
Matteo Reorda 2
Guido Araújo 2
Fei Su 2
Wayne Luk 2
P Chakrabarti 2
Syed Suhaib 1
Andrei Rădulescu 1
Stefanus Mantik 1
Puneet Gupta 1
Fangfang Li 1
Hai Lin 1
Mark Yeary 1
Vissarion Ferentinos 1
Erwan Raffin 1
Dennis Sylvester 1
K Yuan 1
James Huggins 1
Claudio Passerone 1
Alfredo Benso 1
Nakwoong Eum 1
Pengwen Chen 1
Chinchih Chang 1
Chengyen Lin 1
Sudhanshu Vyas 1
Kai Huang 1
Alois Knoll 1
Guolong Chen 1
Annette Bunker 1
Malgorzata Marek-Sadowska 1
Michael Birbas 1
Pierre Paulin 1
Steven Bashford 1
Chris Ostler 1
Gang Wang 1
Guangyu Sun 1
Huazhong Yang 1
Iyad Al Khatib 1
Rustam Nabiev 1
Peter Hawrylak 1
Rensong Tsay 1
Daniel Casarotto 1
Ted Huffmire 1
Jonathan Valamehr 1
Maciek Kormicki 1
Yajun Ha 1
I Tseng 1
Alexander Veidenbaum 1
Zhiwei Qin 1
Xiaowei Li 1
Yuning Chang 1
Rajkumar Raval 1
Matin Hashemi 1
Benjamin Schafer 1
Haifeng Qian 1
Guilherme Flach 1
Yenlung Chen 1
Eamonn O'Toole 1
Carl Pixley 1
Hai Li 1
Wooyoung Jang 1
Jiang Hu 1
Marc Geilen 1
Marie Flottes 1
Alex Jones 1
Yang Xu 1
Libo Huang 1
Jongwon Lee 1
Rico Backasch 1
Jason Oberg 1
Baolei Mao 1
Seungcheol Baek 1
Chrysostomos Nicopoulos 1
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Sam Bayless 1
Bojan Maric 1
Xuandong Li 1
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Duo Liu 1
Nicolas Blanc 1
Peng Yang 1
Trevor Hodges 1
I Tsai 1
David Landis 1
Seher Kiziltepe 1
Guanying Wu 1
Xubin He 1
Xi Chen 1
Sunwook Kim 1
Rafael Rosales 1
William Song 1
Chen Huang 1
Pei Zhang 1
Huazhong Yang 1
Saeed Safari 1
Kuanhsien Ho 1
Katrina Lu 1
Kun Yuan 1
Dimitris Nikolos 1
Guilherme Ottoni 1
Min Zhao 1
Szuchi Wang 1
Shijie Wen 1
Jianchao Lu 1
David Kidd 1
Scott Van Sooy 1
Vijay Pitchumani 1
Ivan Hom 1
Gert Goossens 1
Dirk Lanneer 1
Teemu Pitkänen 1
Joan Carletta 1
Mehrdad Nourani 1
Hirofumi Shinohara 1
Luc Bianco 1
Giuseppe Mangioni 1
Marcus Schmitz 1
Bashir Al-Hashimi 1
Pradip Jha 1
Miron Abramovici 1
Zhanglei Wang 1
Cécile Belleudy 1
Frédéric Rousseau 1
Trongyen Lee 1
Wolfgang Rosenstiel 1
François Boyer 1
Jeroen Voeten 1
João Marques-Silva 1
TaiHung Liu 1
Moonjung Chung 1
ThuydM Le 1
Chauchin Su 1
Chidamber Kulkarni 1
Abhijit Chatterjee 1
Andy Yan 1
Angchih Hsieh 1
Gustavo Neuberger 1
Manoj Sachdev 1
Adit Singh 1
John Pape 1
Eren Kursun 1
Siobhán Clarke 1
Hongting Lin 1
Padmaraj Singh 1
Michael Kishinevsky 1
Jean Rolt 1
Scott Chilstedt 1
Siddharth Jain 1
Jinho Lee 1
Rohit Ramanujam 1
Bill Lin 1
Bo Wang 1
Wonyong Sung 1
Mehrdad Majzoobi 1
Duo Li 1
Michael Gester 1
Baoxian Zhao 1
Amit Agarwal 1
Yosinori Watanabe 1
Renshen Wang 1
Michele Malgeri 1
Maciej Ciesielski 1
Marios Papaefthymiou 1
Anshul Kumar 1
Swarup Das 1
Laurent Freund 1
Kumar Lalgudi 1
Michael Münch 1
Franc Breglez 1
Ismed Hartanto 1
J Lee 1
Giri Tiruvuri 1
W Fuchs 1
Kuangchien Chen 1
Koen Danckaert 1
Noureddine Chabini 1
Michael Gasteier 1
Steven Levitan 1
Dirk Niggemeyer 1
Tsuangwei Chang 1
Bilge Akgul 1
Gregory Dimitroulakos 1
Hyunggyu Lee 1
Pu Liu 1
Hsiangyu Lu 1
Yiran Chen 1
Ulf Schlichtmann 1
Bernd Wurth 1
Olivier Sentieys 1
Frédéric Vivien 1
Paul Chau 1
Pai Chou 1
Saket Gupta 1
Sartaj Sahni 1
Anjur Krishnakumar 1
Jiang Hu 1
Vilasita Kuntamukkala 1
Sotirios Xydis 1
George Economakos 1
Nicholas Imbriglia 1
Giovanni De Micheli 1
Sherief Reda 1
Takeshi Yamamoto 1
John Lee 1
Dana Price 1
Xiang Lu 1
Soumendu Bhattacharya 1
Fernanda De Lima 1
Min Xie 1
Krishna Palem 1
Eugenio Villar 1
Youngpyo Joo 1
SungKyu Lim 1
Wei Wu 1
Román Hermida 1
Nizar Dahir 1
Terrence Mak 1
Jianhua Li 1
Liang Shi 1
Mitchell Thornton 1
Mario Leung 1
Ryan Rakib 1
Muhammad Pasha 1
Amit Chowdhary 1
John Lillis 1
João Marques-Silva 1
Alan Su 1
YuHsin Kuo 1
Furshing Tsai 1
Junxia Ma 1
Gianpiero Cabodi 1
Debapriya Chatterjee 1
Yiding Han 1
Antonio Pérez 1
Yiwen Shi 1
R Iris Bahar 1
Shravan Muddasani 1
Srinivas Boppu 1
John Lee 1
Luca Benini 1
Hiroyuki Kondo 1
Zhe Feng 1
Zhigang Mao 1
Cong Xu 1
Stavros Hadjitheophanous 1
Shimeng Yu 1
Mohammad Samavatian 1
Yingchi Li 1
Anand Raghunathan 1
Ran Wang 1
Praveen Murthy 1
Joonho Kong 1
George Kornaros 1
Richard Lasslop 1
Jens Vygen 1
Qing Wu 1
M Joseph 1
Yenpo Ho 1
John Jose 1
Alain Girault 1
Wenli Shih 1
Lingyi Liu 1
Harald Søndergaard 1
Peter Stuckey 1
Francisco Cazorla 1
Chiara Sandionigi 1
Srijan Kumar 1
Fangming Ye 1
Pohsun Wu 1
Laleh Behjat 1
Yu Cao 1
Sobhanbabu Ch 1
Bowen Zheng 1
Ye Zhang 1
Changhao Yan 1
Xuan Zeng 1
Fabian Oboril 1
Gilberto Ochoa-Ruiz 1
ZoltánÁdám Mann 1
Mohammad Tehranipour 1
Turker Kuyel 1
Tim Kong 1
Lakshmi Chakrapani 1
Ra'ed Al-Dujaily 1
Jason Tong 1
Raid Ayoub 1
V Nair 1
Charalambos Ioannides 1
Steven Derrien 1
Robert Schreiber 1
Meenakshi Kaul 1
Alex OrailoĞLu 1
Weikai Cheng 1
Fang Gong 1
Sehwan Kim 1
Ashok Sudarsanam 1
Jinjun Xiong 1
Peiyu Huang 1
Xijiang Lin 1
Jie Gong 1
Les Walczowski 1
Dilvan Moreira 1
Venkat Thanvantri 1
Andrew DeOrio 1
Antara Ain 1
Shangping Ren 1
J Van Eijnhoven 1
Moritz Schmid 1
Sandip Kundu 1
Ryan Cochran 1
Juyueh Lee 1
Weifeng He 1
Atsuto Hanami 1
Renyuan Zhang 1
Gary Tressler 1
Hyungjun Kim 1
Arseniy Vitkovskiy 1
Hamid Sarbazi-Azad 1
Steffen Peter 1
Changho Choi 1
Brentbyunghoon Kang 1
Alex Doboli 1
Zainalabedin Navabi 1
David Berner 1
Calin Ciordas 1
Hai Lin 1
Chungki Oh 1
Chunan Chen 1
Garng Huang 1
Chunkai Wang 1
Chingyu Chin 1
Dejun Mu 1
Mohit Tiwari 1
Xueliang Li 1
Farshad Firouzi 1
Tian Zhang 1
Savithri Sundareswaran 1
Fahimeh Jafari 1
Xin Li 1
Taemin Lee 1
Hyunsun Park 1
Junwhan Ahn 1
Tomvander Aa 1
Saraju Mohanty 1
James Geraci 1
Priyank Gupta 1
Seetal Potluri 1
A Trinadh 1
Sebastien Guillet 1
Éric Rutten 1
Jean Diguet 1
Kiyin Chang 1
Ian Parberry 1
Chichou Kao 1
Saurabh Adya 1
Yehia Massoud 1
Qingfeng Zhuge 1
PoHsien Chang 1
WeiChung Chao 1
Sunil Chappidi 1
Song Liu 1
Ge Yu 1
Javier Resano 1
Daniel Mozos 1
KuangCyun Hsiao 1
Jingwei Lu 1
Chulhong Park 1
Sayantan Das 1
Michael Taylor 1
Yenchun Lin 1
Qinke Wang 1
SueHong Chow 1
Guoqing Chen 1
David Hély 1
Liang Chen 1
Yongpan Liu 1
Eddie Hung 1
Song Jin 1
Huawei Li 1
Karin Avnit 1
Sudeep Pasricha 1
Yuru Hong 1
Owen Farell 1
Philippe Grosse 1
Yves Durand 1
Sanghyeon Baeg 1
Weitsun Sun 1
Sungkyu Lim 1
Kunhyuk Kang 1
Jason Cheatham 1
Mauricio Ayala-Rincón 1
Hannahhonghua Yang 1
Qiang Zhou 1
Paul Pop 1
Traian Pop 1
Petru Eles 1
Swanwa Liao 1
Xue Liu 1
Gunar Schirner 1
Andreas Gerstlauer 1
Somnath Paul 1
Heman Khanna 1
Yuan Cai 1
David Long 1
Mahesh Iyer 1
Xiaojian Yang 1
Stefan Obenaus 1
Fabrizio Lombardi 1
Kumar Parthasarathy 1
Naran Sirisantana 1
Hiren Patel 1
YoungMin Yi 1
Tathagato Dastidar 1
Lingling Jin 1
Pablo Del Valle 1
Giacomo Paci 1
Alex Yakovlev 1
Yinlong Xu 1
Christoph Kern 1
Zhaoliang Pan 1
Jay Roy 1
Wei Zhao 1
Hungyi Li 1
Vladimir Zolotov 1
Jay Brockman 1
Mohammed Khatib 1
Bijan Alizadeh 1
Jiunlang Huang 1
AnPing Wang 1
Pai Chou 1
Tiansi Hu 1
Jinjun Xiong 1
YongHwan Kim 1
ChoonYik Tang 1
Waichung Tang 1
Robert Dick 1
David Blaauw 1
ChunDa Du 1
D Van Campenhout 1
Trevor Mudge 1
Rick McGeer 1
Miad Faezipour 1
Chunghsiang Lin 1
Byunghyun Lee 1
Ilia Polian 1
Zhihua Zhou 1
Dennis Huang 1
Chungkuan Cheng 1
Dong Lee 1
Ken Kennedy 1
Sharat Prasad 1
Xing Huang 1
Yuzheng Ding 1
David Whalley 1
ChuangYi Chiu 1
Navin Vemuri 1
Rajeev Jayaraman 1
Andreas Hoffmann 1
Scott Mahlke 1
Ingjer Huang 1
Bruno Lavigueur 1
Geert Deconinck 1
Hsueh Lu 1
Peter Milder 1
Davide Bertozzi 1
Kishore Muchherla 1
Panagiotis Manolios 1
Nobuhiro Tsuda 1
Luiz Santos 1
Donatella Sciuto 1
Brett Brotherton 1

Affiliation Paper Counts
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
Macau University of Science and Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
Huawei Technologies Co., Ltd. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
North China Electric Power University 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Microsoft Research 1
University of Potsdam 1
Beijing University of Chemical Technology 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers University 1
Nortel Networks 1
Institute of Computing Technology Chinese Academy of Sciences 1
Curtin University of Technology, Perth 1
Indian Institute of Technology Roorkee 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Gonzaga University 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Texas at San Antonio 1
Universite de Bretagne-Sud 1
China National Petroleum Corporation 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
Hong Kong University of Science and Technology 1
University of Kansas 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
University of Kaiserslautern 1
Nanjing University of Science and Technology 1
University of Kent 1
Auburn University 1
Oakland University 1
INRIA Rhone-Alpes 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Peking University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Washington State University Tri-Cities 1
National Taipei University 1
Michigan Technological University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
Advanced Micro Devices, Inc. 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
East China Normal University 1
Villanova University 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
University of Houston 2
Universitat Politecnica de Catalunya 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
University of Tubingen 2
Southern Methodist University 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
New York University 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Swiss Federal Institute of Technology, Zurich 2
Alcatel-Lucent 2
Stony Brook University 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institute for Research in IT and Random Systems 2
University of Pisa 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
New York University Abu Dhabi 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Korea University 3
University of Electronic Science and Technology of China 3
Bogazici University 3
Delft University of Technology 3
The University of Hong Kong 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
RWTH Aachen University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
Portland State University 3
Hanyang University 3
University of Brasilia 3
University of Melbourne 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Milan 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
Hunan University 3
University of Seville 3
University of Cyprus 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Zhejiang University 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
Louisiana State University 4
Chung Hua University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
Microsoft 4
IBM Austin Research Laboratory 4
Syracuse University 4
Universite de Rennes 1 4
Pohang University of Science and Technology 4
University of Dortmund 4
Ulsan National Institute of Science and Technology 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
Western Michigan University 5
Royal Institute of Technology 5
University of Calgary 5
Instituto Superior Tecnico 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
National University of Singapore 5
Fuzhou University 5
University of Bristol 5
University of North Texas 5
Agilent Technologies 5
Shanghai Jiaotong University 5
Swiss Federal Institute of Technology, Lausanne 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Indian Institute of Technology, Delhi 5
Nanjing University 5
Fujitsu America, Inc. 5
Universite Grenoble Alpes 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
North Carolina State University 6
University of Illinois 6
Nanyang Technological University 6
Fudan University 6
Brown University 6
University of California, Davis 6
Holst Centre 6
University of Connecticut 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
Indian Institute of Technology, Madras 6
National Taiwan University of Science and Technology 6
University of Bologna 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
Universidade de Lisboa 6
McGill University 7
University of Minnesota System 7
Linkoping University 7
HP Labs 7
University of Florida 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Technical University of Munich 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
University of California, Santa Cruz 7
State University of Campinas 7
Utah State University 7
University of Wisconsin Madison 7
Iowa State University 8
Northwestern University 8
Federal University of Santa Catarina 8
University of Science and Technology of China 8
Indian Statistical Institute, Kolkata 8
University of Utah 8
Broadcom Corporation 8
Southern Illinois University at Carbondale 8
Karlsruhe Institute of Technology 8
University of Michigan 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
University of Waterloo 9
Drexel University 9
Freescale Semiconductor 9
University of Notre Dame 9
National Central University Taiwan 9
University of Freiburg 9
University of Illinois at Chicago 9
The University of British Columbia 10
Yuan Ze University 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
National University of Defense Technology China 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
Chung Yuan Christian University 10
NEC Corporation 10
Korea Advanced Institute of Science & Technology 10
Princeton University 11
University of Massachusetts Amherst 11
Imperial College London 11
University of Tehran 11
Samsung Electronics 12
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
Academia Sinica Taiwan 12
University of Texas at Dallas 13
University of Patras 13
University of South Florida Tampa 14
Catholic University of Leuven 14
Complutense University of Madrid 14
University of Southern California 14
National Chung Cheng University 15
University of California, Berkeley 15
University of Erlangen-Nuremberg 16
Chinese Academy of Sciences 16
University of Arizona 17
Pennsylvania State University 18
IBM 18
Virginia Tech 18
Cadence Design Systems 18
Ghent University 18
Chinese University of Hong Kong 19
Arizona State University 19
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
University of California, Santa Barbara 21
National Cheng Kung University 24
Tsinghua University 24
University of Maryland 26
Eindhoven University of Technology 26
Synopsys Incorporated 28
Duke University 30
University of Texas at Austin 30
Intel Corporation 30
Interuniversity Micro-Electronics Center at Leuven 31
Purdue University 32
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
University of Pittsburgh 36
Carnegie Mellon University 36
University of California, Riverside 39
National Taiwan University 40
National Chiao Tung University Taiwan 43
University of California, San Diego 43
Texas A and M University 44
Indian Institute of Technology, Kharagpur 45
University of California, Irvine 63
Seoul National University 64
National Tsing Hua University 64
University of California, Los Angeles 65

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Volume 21 Issue 3, April 2016  Issue-in-Progress
Volume 21 Issue 2, January 2016

Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Volume 20 Issue 3, June 2015
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Volume 20 Issue 1, November 2014
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Volume 19 Issue 1, December 2013
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Volume 18 Issue 3, July 2013
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Volume 17 Issue 4, October 2012
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Volume 17 Issue 2, April 2012
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Volume 16 Issue 4, October 2011
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Volume 16 Issue 1, November 2010
Volume 15 Issue 4, September 2010
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Volume 15 Issue 1, December 2009
Volume 14 Issue 4, August 2009
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Volume 13 Issue 4, September 2008
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Volume 12 Issue 4, September 2007
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Volume 9 Issue 4, October 2004
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Volume 8 Issue 4, October 2003
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Volume 7 Issue 4, October 2002
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Volume 6 Issue 4, October 2001
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Volume 5 Issue 4, Oct. 2000
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Volume 5 Issue 1, Jan. 2000

Volume 4 Issue 4, Oct. 1999
Volume 4 Issue 3, July 1999
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Volume 3 Issue 4, Oct. 1998
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Volume 3 Issue 2, April 1998
Volume 3 Issue 1, Jan. 1998

Volume 2 Issue 4, Oct. 1997
Volume 2 Issue 3, July 1997
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Volume 2 Issue 1, Jan. 1997

Volume 1 Issue 4, Oct. 1996
Volume 1 Issue 3, July 1996
Volume 1 Issue 2, April 1996
Volume 1 Issue 1, Jan. 1996
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