ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

Streaming Sorting Networks

Sorting is a fundamental problem in computer science and has been studied extensively. Thus, a large variety of sorting methods exist for both software and hardware implementations. For the latter, there is a trade-off between the throughput achieved and the cost (i.e., the logic and storage invested to sort n elements). Two popular solutions are... (more)

Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection

Accurately estimating the failure region of rare events for memory-cell and analog circuit blocks under process variations is a challenging task. In... (more)

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression

The clock networks of many modern circuits have to operate in multiple corners and multiple modes... (more)

A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition Using Wearables

Wearables are being widely utilized in health and wellness applications, primarily due to the recent... (more)

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon... (more)

On Battery Recovery Effect in Wireless Sensor Nodes

With the perennial demand for longer runtime of battery-powered Wireless Sensor Nodes (WSNs),... (more)

Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques

The development of enhanced modeling techniques for the simulation of switched-mode Pulse Width... (more)

Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs

This article introduces a Cyber-physical Co-Simulation Framework (CPCSF) for design and analysis of... (more)


With the advent of globalization in the semiconductor industry, it is necessary to prevent unauthorized usage of third-party IPs (3PIPs), cloning and unwanted modification of 3PIPs, and unauthorized production of ICs. Due to the increasing complexity of ICs, system-on-chip (SoC) designers use various 3PIPs in their design to reduce time-to-market... (more)

Timing Path-Driven Cycle Cutting for Sequential Controllers

Power and performance optimization of integrated circuits is performed by timing-driven algorithms that operate on directed acyclic graphs. Sequential... (more)

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

In this article, we derive a simple and accurate expression for the change in timing yield due to a... (more)

Ensemble Reduction via Logic Minimization

An ensemble of machine learning classifiers usually improves generalization performance and is useful for many applications. However, the extra memory storage and computational cost incurred from the combined models often limits their potential applications. In this article, we propose a new ensemble reduction method called CANOPY that... (more)


Best Paper Award: Congratulations to Chung-Wei Lin, Bowen Zheng, Qi Zhu, and Alberto Sangiovanni-Vincentelli on receiving the 2016 ACM TODAES Best Paper Award for their article titled Security-Aware Design Methodology and Optimization for Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1, Article 18, November 2015.

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

Forthcoming Articles
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), the on-chip networks are facing serious challenges in providing fast communication for various tasks and cores. One promising on-chip network design shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behav-iors, both of which have not been fully exploited in existing mapping algorithms. In this paper, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened but-terfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

Hierarchical Statistical Leakage Analysis and Its Application

In this paper, we investigate a hierarchical statistical leakage analysis design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power analysis. To solve the challenges of incorporating spatial correlations between IP modules at system level, we first propose a method to extract correlation-inclusive leakage models. Then a method to handle the spatial correlations at system level is also proposed. Using this method the runtime of system statistical leakage analysis can be significantly improved without disclosing the netlists of the IP modules. Experimental results demonstrate that the proposed hierarchical statistical leakage analysis method is about 100 times faster than the gate-level full-chip statistical leakage analysis methods while the accuracy of statistical leakage analysis is still well maintained. In addition, we also investigate one application of this hierarchical statistical leakage analysis method, a leakage-yield-driven floorplanning framework, to demonstrate the benefits of such hierarchical statistical leakage analysis method in practice. At the same time, we also propose an optimized hierarchical leakage analysis method dedicated for the floorplanning framework. The effectiveness of the floorplanning framework and the optimized method is also confirmed by the experimental results.

Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow

The Scenario-Aware Dataflow (SADF) model is based on concurrent actors that interact via channels. It combines streaming data and control to capture scenarios while incorporating hard and soft real-time aspects. To model data-flow computations that are subject to uncertainty, SADF models are equipped with random primitives. We propose to use probabilistic model checking to analyse uncertain SADF models. We show how measures such as expected time, long-run objectives like throughput, as well as timed reachability can a given system configuration be reached within a deadline with high probability?can be automatically determined. The crux of our method is a compositional semantics of SADF with exponential agent execution times combined with automated abstraction techniques akin to partial-order reduction. We present the semantics in detail, and show how it accommodates the incorporation of execution platforms enabling the analysis of energy consumption. The feasibility of our approach is illustrated by analysing several quantitative measures of an MPEG-4 decoder and an industrial face recognition application.

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems

During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of non-volatile flash in the systems memory hierarchy. The increasing capacity of NAND flash memory introduces large RAMfootprint to store the logical to physical address mapping. The demand-based approach can effectively reduce and well control the RAM footprint. However, extra address translation overhead is also introduced which may degrade the system performance. In this paper, we present CDFTL, an adaptive Caching mechanism for Demand-based Flash Translation Layer, for NAND flash memory storage systems. CDFTL adopts both the fine-grained entry-based caching mechanismto exploit temporal locality and the coarse-grained translation-page-based cachingmechanism to exploit spatial locality of workloads. By selectively caching the on-demand address mappings and adaptively changing the space configurations of two granularities, CDFTL can effectively utilize the RAM space and improve the cache hit ratio. We evaluate CDFTL under a real hardware embedded platform using a variety of I/O traces. Experimental results show that our technique can achieve a 11.13% reduction in average system response time and a 35.21% reduction in translation block erase counts compared with the previous work.

Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors

It is challenging to manage the thermal behavior of many-core microprocessors while still keep it running at high-performance since control complexity increases as core number increases. In this paper, a novel hierarchical dynamic thermal management method is proposed to overcome this challenge. The new method employs model predictive control (MPC) with task migration and DVFS scheme to ensure smooth control behavior and negligible computing performance sacrifice. In order to be scalable to many-core system, the hierarchical control scheme is designed with two levels. At the lower level, the cores are spatially clustered into blocks, and local task migration is used to match current power distribution with the optimal distribution calculated by MPC. At the upper level, global task migration is used with the unmatched powers from the lower level. A modified iterative minimum cut algorithm is used to assist the task migration decision making if the power number is large at the upper level. Finally, DVFS is applied to regulate the remaining unmatched powers. Experiments show that the new method is highly scalable to many-core microprocessors with little computing performance compromises and outperforms existing methods.

A Fast and Scalable Multi-dimensional Multiple-choice Knapsack Heuristic

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredicatability is an important security feature of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In existing literature on PUFs, Hamming Distance test, denoted by HDT(t), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC(t). The objective of these test schemes is to estimate the output transition probability when there are t or less than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test which is denoted as HDT(e,t). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t. As a contribution, we provide a comprehensive discussion and analytic interpretation of the HDT(t), PC(t) and HDT(e,t) test schemes for Arbiter PUF (APUF), XOR PUF and Lightweight Secure PUF (LSPUF). Our analysis establishes that the HDT(e,t) test is more general in comparison with HDT(t) and PC(t) tests. In addition, we demonstrate scenarios where the adversary can exploit the information obtained from the analysis of HDT(e,t) properties of APUF, XOR PUF and LSPUF to develop statistical attacks on them, if the ideal value of HDT(e,t)=0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and FPGA implemented APUF, XOR PUF and LSPUF designs.

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip

Digital (droplet-based) microfluidic technology offers an attractive platform for implementing a wide variety of biochemical laboratory protocols, such as point-of-care diagnosis, DNA analysis, target detection, and drug discovery. However, because of the inherent uncertainty of fluidic operations, the outcome of biochemical experiments performed on-chip can be erroneous even if the chip is tested a priori and deemed to be defect-free. In this paper, we address an important error-recoverability problem in the context of sample preparation. We assume a cyberphysical environment, in which the physical errors, when detected online at selected checkpoints with integrated sensors, can be corrected through recovery techniques. However, almost all prior work on error recoverability used a checkpointing-based rollback approach, i.e., re-execution of certain portion of the protocol starting from the previous checkpoint. Unfortunately, such techniques are expensive both in terms of assay-completion time and reagent cost, and can never ensure full error-recovery in a deterministic sense. We consider imprecise droplet mix-split operations and present a novel roll-forward approach where the erroneous droplets, thus produced, are used in the error-recovery process, instead of being discarded or re-mixed. All erroneous droplets participate in the dilution process and they mutually cancel or reduce the concentration error when the target droplet is reached.We also present a rigorous analysis that discovers the role of volumetric error on the concentration of a sample to be prepared, and we describe the layout of a lab-on-chip that can execute the proposed cyberphysical dilution algorithm. Our analysis reveals that fluidic errors caused by unbalanced droplet splitting can be classified as being either critical or non-critical, and only those of the former type require correction to achieve error-free sample dilution. Simulation experiments on various sample preparation test cases demonstrate the effectiveness of the proposed method.

ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems

Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and QoS guarantees on multiprocessors, form an attractive alternative in real-time embedded systems that concurrently run a mix of independent applications with varying timeliness constraints. This paper presents "ERfair Scheduler with Suspension on Multiprocessors" (ESSM), an efficient, optimal proportional fair scheduler that attempts to reduce system wide energy consumption by locally maximizing the processor suspension intervals while not sacrificing the ERfairness timing constraints of the system. The proposed technique takes advantage of higher execution rates of tasks in underloaded ERfair systems and uses a procrastination scheme to search for time points within the schedule where suspension intervals are locally maximal. Evaluation results reveal that ESSM achieves good sleep efficiency and provides upto 50% higher effective total sleep durations as compared to the Basic-ERfair scheduler on systems consisting of 2 to 20 processors.

Non-enumerative Generation of Path Delay Distributions and its Application to Critical Path Selection

A Monte Carlo based approach is proposed capable of identifying in a path-implicit and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

System Level Design Approaches to Security in Automotive Networks

With the increasing amount of interconnections between vehicles, the attack surface of internal vehicle networks is rising steeply. Although these networks are shielded against external attacks, they often do not have any internal security to protect against malicious components or adversaries who can breach the network perimeter. To secure the in-vehicle network, all communicating components must be authenticated, and only authorized components should be allowed to send and receive messages. This is achieved through an authentication framework. Cryptography is widely used to authenticate communicating parties and provide secure communication channels (e.g. Internet communication). However, real-time performance requirements of in-vehicle networks restrict the types of cryptographic algorithms and protocols that may be used. In particular, asymmetric cryptography is computationally infeasible during vehicle operation. In this work, we address the challenges of designing authentication protocols for automotive systems. We present Lightweight Authentication for Secure Automotive Networks (LASAN), a full life-cycle authentication approach. We describe the LASAN protocols and show how they protect the internal vehicle network while complying with the real-time constraints and low computational resources of this domain. Unlike previous work, we also explain how LASAN can be integrated into all aspects of the automotive product life cycle, including manufacturing and maintenance. We evaluate LASAN in two ways: Firstly, we analyze the security of the protocols using established protocol verication based on formal methods. Secondly, we evaluate the timing requirements of LASAN and compare these to other frameworks using a new discrete event simulator for in-vehicle networks.

A Compact Implementation of Salsa20 and its Power Analysis Vulnerabilities

In this paper, we present a compact implementation of Salsa20 stream cipher that is targeted towards lightweight cryptographic devices such as RFID tags. The Salsa20 stream cipher, an ARX cipher, is used in high security cryptography in NEON instruction set embedded in ARM-based tablets and smartphones. The existing literature shows that though classical cryptanalysis has been effective on reduced rounds of Salsa20, the stream cipher is immune to software side-channel attacks such as branch timing and cache timing attacks. To the best of our knowledge, this work is the first to perform hardware power analysis attacks, where we evaluate the resistance of all the eight keywords in the proposed compact implementation of Salsa20. Our technique targets the three subrounds of the first round of the implemented Salsa20. The CPA attack has an attack complexity of $2^{19}$. Based on extensive experiments on a compact implementation of Salsa20, we demonstrate that all these keywords can be recovered within $20000$ queries on Salsa20. The attacks show a varying resilience of the key words against correlation power analysis (CPA) that has not yet been observed in any stream or block cipher in present literature. This makes the architecture of this stream cipher interesting from the side-channel analysis perspective. Also, we propose a light-weight countermeasure which mitigates the leakage in the power traces as shown in the results of Welch's $t$-test statistics. The hardware area overhead of the proposed countermeasure is only $14\%$ and is designed with compact implementation in mind.

DReAM: an Approach to Estimate Per-Task DRAM Energy in Multicore Systems

Per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction between tasks in shared resources, which impacts tasks' energy consumption in uncontrolled ways. Some accurate mechanisms have been devised recently to estimate per-task energy consumed on-chip in multicores, but there is a lack of such mechanisms for DRAM memories. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations. In particular, the contributions of this paper are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate, yet low cost, implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is more accurate than these other methods

Path Selection for Real-Time Communication on Priority-Aware NoCs

This work investigates selecting paths for communication flows when deploying a hard real-time application on a chip-multiprocessor system. This chip-multiprocessor system uses a priority-aware real-time network-on-chip interconnect between the processors. Given a mapping of the computation tasks onto the chip-multiprocessor, the problem we address in this work is to discover paths the communication flows take such that hard real-time deadlines of flows are met. Furthermore, we must ensure that deadlines are met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a stage-level analysis for real-time communication to determine the impact of a network link being used by a flow, and its effect on other flows sharing the link. The path selection algorithm uses heuristics such as selecting links with least interference, and considering lower priority flows when dedicating links to paths of higher priority flows since an optimal one is intractable. The algorithm also considers constraints on the number of virtual channels at each router port in the network. The statistically significant experimental results show an improvement in schedulability by 5% and 12% over existing path selection algorithms such as Minimum Interference Routing and Widest Shortest Path algorithms, respectively. We also present a set-top box case study to further illustrate the benefits of using the proposed algorithm.

Area-aware Decomposition for Single-Electron Transistor Arrays

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moores law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large reconfigurable SET array where the height of SET array equals the number of primary inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say 10, rather than arbitrary value due to the ultra-low driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large SET array into a set of small SET arrays where each of them realizes a subfunction of the original circuit with no more than 10 inputs. Thus, this paper presents two techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced. The width minimization algorithm leads to a 25%~41% improvement compared to the state-of-the-art, and the mapping algorithm achieves a 60% reduction in total area compared to a nai1ve approach.

Improving PCM Endurance with a Constant-cost Wear Leveling Design

Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling is an effective way to improve PCM endurance, but its major challenge is how to efficiently determine the appropriate memory pages for allocation or swapping. In this paper, we present a constant-cost wear leveling design that is compatible with existing memory management. Two implementations, namely bucket-based and array-based wear leveling, with constant-time (or nearly zero) search cost are proposed to be integrated into the OS layer and the hardware layer respectively, as well as to trade between time and space complexity. The results of experiments conducted based on an implementation in Android, as well as simulations with popular benchmarks, to evaluate the effectiveness of the proposed design are very encouraging.

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement

Routability is one of the most important problems in high performance circuit designs. From the viewpoint of placement design, two major factors cause routing congestion: 1) interconnections between cells, and 2) connections on macro blockages. In this paper, we present a routability-driven placer Ripple 2.0 which emphasizes both kinds of routing congestion. Several techniques will be presented, including 1) cell inflation with routing path consideration, 2) congested cluster optimization, 3) routability-driven cell spreading, and 4) simultaneous routing and placement for routability refinement. With the official evaluation protocol, Ripple 2.0 outperforms other published academic routability-driven placers. Compared with top results in ICCAD 2012 contest, Ripple 2.0 achieves better detailed routing solution obtained by a commercial router.

Hybrid Power Management for Office Equipment

Office machines (such as printers, scanners, fax, and copiers) can consume significant amounts of power. Most office machines have sleep modes to save power. Power management of these machines are usually timeout-based: a machine sleeps after being idle long enough. Setting the timeout duration can be difficult: if it is too long, the machine wastes power during idleness. If it is too short, the machine sleeps too soon and too often the wakeup delay can significantly degrade productivity. Thus, power management is a tradeoff between saving energy and keeping response time short. Many power management policies have been published and one policy may outperform another in some scenarios. There is no definite conclusion which policy is always better. This paper describes two methods for office equipment power management. The first method adaptively reduces power based on a constraint of the wakeup delay. The second method is a hybrid method with multiple candidate policies and it selects the most appropriate power management policy. Using six months of request traces from 18 different printers, we demonstrate that the hybrid policy outperforms individual policies. We also discover that power management based on business hours does not produce consistent energy savings.

Preface to Special Section on New Physical Design Techniques for the Next Generation Integration Technology

Critical-Path-Aware High-Level Synthesis with Distributed Controller for Fast Timing Closure

Floorplanning and Topology Synthesis for Application Specific Network-on-Chips with RF-Interconnect

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on chip communication becomes more and more complex and the power consumption imposes the major challenge for designing ASNoCs. In this paper, we first time propose a four-stage floorplanning and topology synthesis approach for ASNoCs with Radio Frequency Interconnect (RF-I). Firstly, considering the advantage of RF-I in long distance on-chip communication, we integrate the floorplanning and clustering to explore the optimal clustering of cores, where the cores belonging to the same cluster will share the same switch for communications, form an island, and occupy a contiguous physical region. After the switches and network interfaces are inserted into the floorplan, the allocation of routing paths and the RF-I logical channels are integrated in an iterative procedure to generate fine-grain dynamically reconfigurable ASNoC topologies. Finally, considering the signal integrity of RF-I, we adjust the placement of the switches by a simulated annealing-based method to reduce the number of the RF-I routing corners. To evaluate the placement of switches, we propose a dynamical programming based method to route the transmission line and count the routing corners in linear time. The results show that, using RF-I, we can reduce the power consumption of ASNoCs by 20%-29%.

Partitioning and Data Mapping in Reconfigurable Cache and ScratchPad Memory based Architectures

Scratch Pad memory (SPM) is considered a useful component in the memory hierarchy, solely or along with caches, to meet the power and energy constraints as performance ceases to be the sole criteria for processor design. Although the efficiency of SPM is well known, its usage has been restricted owing to difficulties in programmability. Real applications usually have regions that are amenable to exploitation by either SPM or cache, and hence can benefit if the two are used in conjunction. Dynamically adjusting the local memory resources to suit application demand, can significantly improve the efficiency of the overall system. In this paper, we propose a compiler technique to map application data objects to SPM/cache and also partition the local memory between SPM and cache depending on the dynamic requirement of the application. First, we introduce a novel graph based structure to tackle data allocation in an application. Second, we use this to present a data allocation heuristic to map program objects for a fixed sized SPM-cache hybrid system that targets whole program optimization. We finally extend this formulation to adapt the SPM and cache sizes, as well as the data allocation as per the requirement of different application regions. We study the applicability of the technique on various workloads targeted at both SPM-Only and hardware reconfigurable memory system, and observe an average of 18% energy-delay improvement over state-of-the-art techniques.

Scalable SMT-based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis

In this paper, we present a novel methodology based on SMT-solvers to verify equality of a high level described specification and a pipelined RTL implementation produced by a high level synthesis tool. The complex transformations existing in the high level synthesis process, such as nested loop pipelining, cause the conventional methods of equivalence checking to be inefficient. The proposed equivalence checking method attacks simultaneously to the two problems in this context: 1) state space explosion and 2) complex high level synthesis transformations. To show the scalability and efficiency of the proposed method, the verification results of large industrial designs are compared with those of the SAT-based method, including three different state-of-the-art SAT-solvers, the SMT-based procedure, the modular Horner expansion diagram (M-HED) based method, and the M-HED partitioning approach. The results show interesting improvements in terms of time and memory usage in comparison with other methods. Furthermore, using the proposed equivalence checking approach, fault tolerance issues can be formally analyzed in the presence of some faults in the designs.

Genetic Algorithm Based FPGA Architectural Exploration using Analytical Models

FPGA architectural optimization has emerged as one of the most important digital design challenges. Recent years, experimental methods have been replaced by analytical ones to find the optimized architecture. Time is the main reason for this replacement. Conventional Geometric Programming (GP) is a routine framework to solve analytical models; including area, delay and power models. In this paper, we discuss the application of Genetic Algorithm (GA) to the design of FPGA architectures. The performance model has been integrated into the Genetic Algorithm framework in order to investigate the impact of various architectural parameters on the performance-efficiency of FPGAs. This way, we are able to rapidly analyze FPGA architectures and select the best one. The main advantages of using GA versus GP are concurrency and speed. The results show that concurrent optimization of high-level architecture parameters including Look-up Table size (K) and Cluster size (N) and low-level parameters like scaling of transistors is possible for GA, whereas GP does not capture K and N under its concurrency and it needs to exhaustively search all possible combinations of K and N. The results also show that up to 104´ run time improvement in comparison with GP based analysis is achieved.

Reducing the Complexity of Dataflow Graphs using Slack-based Merging

There exist many dataflow applications with timing constraints that require real-time guarantees on safe execution without violating their deadlines. Extraction of timing parameters (offsets, deadlines, periods) from these applications enables the use of real-time scheduling and analysis techniques, and provides guarantees on satisfying timing constraints. However, existing extraction techniques require the transformation of the dataflow application from highly expressive dataflow computational models, e.g., Synchronous Dataflow (SDF) and Cyclo-Static Dataflow (CSDF) to Homogeneous Synchronous Dataflow (HSDF). This transformation can lead to an exponential increase in the size of the application graph that significantly increases the run-time of the analysis. In this article, we address this problem by proposing an algorithm called slack-based merging that generates a reduced-size HSDF graph from a given SDF graph with timing constraints. This algorithm is based on a novel concept of merging called safe merge, which is a merge operation that we formally prove that it cannot cause a live HSDF graph to deadlock. The results show that the reduced graph: 1) respects the throughput and latency constraints of the original application graph and 2) typically speeds up the process of extracting timing parameters and finding a feasible real-time schedule for real-time dataflow applications. They also show that when the throughput constraint is relaxed with respect to the maximal throughput of the graph, the merging algorithm is able to achieve a larger reduction in graph size, which in turn results in a larger speed-up of the real-time scheduling algorithms.


Publication Years 1996-2016
Publication Count 862
Citation Count 3970
Available for Download 862
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First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Distinguished Member (2008)
ACM Senior Member (2006)
Nikil D. Dutt ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
Soheil Ghiasi ACM Senior Member (2015)
Matthew Guthaus ACM Senior Member (2013)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
John Lee ACM Senior Member (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Ian Parberry ACM Distinguished Member (2015)
Massoud Pedram ACM Distinguished Member (2008)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
Robert Schreiber ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 17
Nikil Dutt 15
Irith Pomeranz 14
Krishnendu Chakrabarty 12
Jason Cong 12
Tingting Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
Sheldon Tan 9
Lei He 8
Yaowen Chang 8
Yunheung Paek 7
Frank Vahid 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Spyros Tragoudas 6
Taewhan Kim 6
Martin Wong 6
Alexandru Nicolau 6
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Giovanni Beltrame 1
Jeremy Dubeuf 1
Xinyu He 1
Songwei Pei 1
Juinndar Huang 1
Marcelo Cintra 1
Margarida Jacome 1
Tan Yan 1
Ekaterina Kutsy 1
Ofer Strichman 1
Kartikey Mittal 1
Michael Healy 1
André Nácul 1
Zhongzhen Wu 1
Keven Dunn 1
Stanley Baumgart 1
Stylianos Mamagkakis 1
Karthikeyan Lingasubramanian 1
Sandeep Gupta 1
Rajeshkumar Sambandam 1
Tobias Becker 1
Xufa Wang 1
Jun Seomun 1
Takayasu Sakurai 1
Subhashis Majumder 1
Jean Berge 1
Shaoxi Wang 1
Chingwei Yeh 1
Saravanan Padmanaban 1
Chittaranjan Mandal 1
Mohamed Elwakil 1
Joan Lopez 1
ChungHwang Chen 1
Michael Boyer 1
Srikanth Venkataraman 1
Horácio Neto 1
Joseph Shinnerl 1
Qingan Li 1
Esteban Tlelo-Cuautle 1
JyhMou Tseng 1
Wei Jiang 1
Yu Liu 1
Tomtong Jing 1
Robi Dutta 1
Shaz Qadeer 1
Ralph Hasholzner 1
Nong Xiao 1
Stefan Hillebrecht 1
Jiantao Wang 1
Frank Vahid 1
Ankur Srivastava 1
Martin Leucker 1
Renjie Lee 1
Hakan Aydín 1
Wenpin Tu 1
Shiyan Hu 1
Bo Yang 1
Aysa Tabrizi 1
Guojie Luo 1
Youjip Won 1
Yoonseok Yang 1
Samarjit Chakraborty 1
Kyle Stegner 1
Chao Wang 1
Jongchul Lee 1
Zhonghai Lu 1
Adam Kaplan 1
Amit Singh 1
Jhengsyun Yang 1
Tienfu Chen 1
F Johnson 1
Yushih Su 1
Chaitali Chakrabarti 1
Rungbin Lin 1
Bruno Rouzeyre 1
I Tseng 1
Jongeun Lee 1
Rami Melhem 1
Chita Das 1
Sandeep Goel 1
Muhammad Nummer 1
Le Jin 1
Giovanni De Micheli 1
Choonseung Lee 1
Hasan Khalifeh 1
Fang Liu 1
Plamen Nikolov 1
Sandro Rigo 1
Max Schultz 1
Kuenjong Lee 1
Tsungchu Huang 1
Andrew Wolfe 1
Yau Li 1
Klaus Eckl 1
Wanting Lo 1
Chiehjui Lee 1
Chandu Visweswariah 1
Raj Nadakuditi 1
Huankai Peng 1
HsuanMing Huang 1
Paolo Camurati 1
K Tsai 1
Shashidhar Thakur 1
Adrian Ludwin 1
Tiempo Sas 1
Wenjong Fang 1
Vincent Mooney 1
Yuhao Zhu 1
Michael Hsiao 1
James Li 1
Matthew Gately 1
Scott Little 1
David Bild 1
Gregory Bok 1
Gauthier Lafruit 1
Claudio Sansoè 1
Piet Engelke 1
Sally McKee 1
Keshab Parhi 1
Kevin Lepak 1
Gerda Janssens 1
Wenrui Gong 1
Brian DeRenzi 1
Michael Mefenza 1
Hsiangpang Li 1
Jingwei Lu 1
Said Hamdioui 1
Adwait Gupte 1
Nathan Denny 1
J Chen 1
Ausif Mahmood 1
William Hung 1
Sumit Gupta 1
U Rovati 1
Stephen Cauley 1
Ying Hu 1
Yufu Zhang 1
Yu Hu 1
Roberto Cordone 1
Ronny Krashinsky 1
Antonis Papanikolaou 1
Tomas Pecenka 1
Lukáš Sekanina 1
Zdeněk Kotásek 1
Jennifer Dworak 1
Nuno Alves 1
Jürgen Teich 1
Rui Zheng 1
Liang Shi 1
Jianhua Li 1
Harikumar Somakumar 1
Wenyao Xu 1
Syingjyan Wang 1
Katherine Li 1
William Davis 1
Jinsik Kim 1
Seokhyeong Kang 1
Evangelos Eleftheriou 1
Thomas Griffin 1
Bradley Kiddie 1
Daniel Limbrick 1
Xin Huang 1
Ramin Bashizade 1
Youtao Zhang 1
Hadi Esmaeilzadeh 1
Saeed Shamshiri 1
Jef Meerbergen 1
Jef Van Meerbergen 1
Rainer Leupers 1
KunLin Tsai 1
Shanqjang Ruan 1
Péter Arató 1
Donald Gelosh 1
Dorothy Setliff 1
Stephen Blythe 1
Alain Pegatoquet 1
Ramin Hojati 1
Qing Su 1
Patrick Schaumont 1
Ashok Halambi 1
Sharad Sinha 1
Chakchung Cheung 1
Alain Darte 1
Seongook Jung 1
Stephen Edwards 1
Jackey Yan 1
Chris Chu 1
Yongwen Wang 1
Dominik Erb 1
Matthias Sauer 1
Tobias Schubert 1
Minseok Kang 1
Baktash Boghrati 1
Hai Wang 1
Tim Nieberg 1
Ying Tan 1
Ali Pınar 1
José Costa 1
Chuangwen Liu 1
Gwan Choi 1
Haotse Chen 1
Dacheng Juan 1
Diana Marculescu 1
Dip Goswami 1
Linzhang Wang 1
Jean Desbarbieux 1
Emmanuelle Encrenaz 1
Safar Hatami 1
Namita Sharma 1
Ganghee Lee 1
Zheng Xu 1
Hamid Shojaei 1
Youtao Zhang 1
Giorgio Natale 1
Qiang Ma 1
Martin Wong 1
Yaolin Chang 1
Sanghyun Park 1
Yongjoo Kim 1
Yahya Osais 1
Markus Seuring 1
Randall Geiger 1
Degang Chen 1
Pinar Korkmaz 1
Yan Lin 1
Raymond Hoare 1
John Lockwood 1
Sabyasachi Das 1
Krste Asanović 1
Huaizhi Wu 1
Sudarshan Bahukudumbi 1
B Rau 1
Ashok Jagannathan 1
Sungwoo Hur 1
Kan Xiao 1
Hokyoon Lee 1
Florent De Lamotte 1
Andreas Burg 1
Harry Hoster 1
Dani Tannir 1
Bingsheng He 1
Marcela Zuluaga 1
Justin Stander 1
Frederik Vandeputte 1
Stelios Mamagkakis 1
Puneet Sharma 1
Arnab Sinha 1
Bhaskar Pal 1
Yuanfang Hu 1
Yubin Zhang 1
Adam Hartman 1
Daujieu Yang 1
Huihsin Hsu 1
Jenhao Chen 1
Douglas Keller 1
Jongkyung Paek 1
EnShou Chang 1
Yi Xu 1
Kele Shen 1
Zhi Li 1
Vincent Beroulle 1
Mehdi Kamal 1
Xiaobosharon Hu 1
Ibrahim Hajj 1
Vikram Saxena 1
Giovanni Squillero 1
Viktor Lapinskii 1
Gustavo De Veciana 1
Francisco Fernández 1
Chihhung Liu 1
Syyen Kuo 1
Paul Feautrier 1
Xiaofang Wang 1
Xinzhang Jia 1
Filipa Duarte 1
Jun Zhou 1
Hsien Lee 1
Kuohua Wang 1
Ricardo Jacobi 1
Kundan Nepal 1
Francesco Zanini 1
Colin Jones 1
Naifeng Jing 1
Santiago Mok 1
Chaohung Lu 1
Jarrod Roy 1
Nan Guan 1
Carlos González 1
Andrea Calimera 1
Thorlindur Thorolfsson 1
Jiajia Li 1
José Pineda De Gyvez 1
Thomas Mittelholzer 1
Charles Camp 1
Yang Zheng 1
Leila Delshadtehrani 1
Hamed Farbeh 1
Weijian Su 1
Abhishek Koneru 1
Leandro Indrusiak 1
Osmar Dos Santos 1
B Rau 1
Mohammad Tehranipour 1
Edwin Naroska 1
ZoltánÁdám Mann 1
Jamil Kawa 1
Dhananjay Kulkarni 1
Edwin Sha 1
Yehchi Chang 1
Gregor Goessler 1
Wei Hu 1
Chia Yen 1
Mohammed Elshoukry 1
Hongliang Chang 1
Laurence Goodby 1
Luís Guerra E Silva 1
Shi Lin 1
Hemangee Kapoor 1
Dariusz Kania 1
Claudio Talarico 1
Ying Qin 1
Shengyu Shen 1
Huadong Dai 1
Qi Zhu 1
Waishing Luk 1
Zuoyuan Li 1
Tero Rissa 1
Yosinori Watanabe 1
Renshen Wang 1
Anshul Kumar 1
Swarup Das 1
Laurent Freund 1
Michael Münch 1
Mohammad Foroozannejad 1
Chen Li 1
Chris Bleakley 1
Hidehiro Takata 1
Vijaykrishnan Narayanan 1
Hassan Salamy 1
J Lee 1
Giri Tiruvuri 1
Franc Breglez 1
Ismed Hartanto 1
Koen Danckaert 1
Steven Levitan 1
Hsiangyu Lu 1
Yiran Chen 1
Michael Gasteier 1
W Fuchs 1
Kuangchien Chen 1
Noureddine Chabini 1
Bernd Wurth 1
Olivier Sentieys 1
Pai Chou 1
Saket Gupta 1
Sartaj Sahni 1
Anjur Krishnakumar 1
Jiang Hu 1
Vilasita Kuntamukkala 1
Steve Tjiang 1
Nagu Dhanwada 1
Hua Xiang 1
Andrew Cassidy 1
Xiaoqing Wen 1
Arijit Mondal 1
Xiaoqing Yang 1
Yuliang Wu 1
Bert Geelen 1
Jaehyun Kim 1
Rajeev Rao 1
Dinesh Ramanathan 1
David Van Campenhout 1
Samarjit Chakraborty 1
Hongfei Wang 1
Fubing Mao 1
Hai Li 1
Hosoon Shin 1
Qihang Shi 1
Joachim Keinert 1
Christian Haubelt 1
Gayatri Mehta 1
Mustafa Baz 1
Koen De Bosschere 1
Liling Hung 1
Qiang Xu 1
Kunal Ganeshpure 1
Zhongyi Jin 1
Curt Schurgers 1
Zipeng Li 1
Xin Fu 1
Saeed Safari 1
Daming Zhang 1
Pei Zhang 1
Huazhong Yang 1
Kuanhsien Ho 1
Katrina Lu 1
Dimitris Nikolos 1
Min Zhao 1
Guilherme Ottoni 1
Szuchi Wang 1
Shijie Wen 1
Jianchao Lu 1
David Kidd 1
Scott Van Sooy 1
Vijay Pitchumani 1
Ivan Hom 1
Gert Goossens 1
Dirk Lanneer 1
Joan Carletta 1
Mehrdad Nourani 1
Teemu Pitkänen 1
Zhanglei Wang 1
Marcus Schmitz 1
Bashir Al-Hashimi 1
Cécile Belleudy 1
Frédéric Rousseau 1
Hirofumi Shinohara 1
Jayanta Bhadra 1
John Pape 1
Xiaoke Qin 1
Hussain Al-Asaad 1
Rina Panigrahy 1
Jonathan Martin 1
Hao Li 1
Vijay Sundararajan 1
Juan Lanchares 1
Rajiv Gupta 1
E Mariatos 1
Christophe Bobda 1
Tianshi Chen 1
Olivier Temam 1
Depei Qian 1
Hungsheng Chang 1
Salvador Mir 1
YannRue Lin 1
Hsinhung Lin 1
Yoshiaki Fukui 1
Yihlang Li 1
Mohamed Zahran 1
Douglas Myers 1
Robert Brayton 1
Jonghee Youn 1
Yuan Yuan 1
Christian Hochberger 1
Alexander Weiss 1
Christian Panten 1
Dakai Zhu 1
Qing Dong 1
David Westwick 1
Renan Netto 1
Jian Kuang 1
Chuansheng Dong 1
Haibo Zeng 1
Yoan Lin 1
Unmesh Bordoloi 1
Petru Eles 1
Marcelo Johann 1
Qiuping Yi 1
Zili Shao 1
Dhiraj Pradhan 1
Chaowen Tzeng 1
Kueichung Chang 1
Jihsheng Shen 1
Joachim Anlauf 1
Sami Taktak 1
Zhiliang Qian 1
Robert Elio 1
Jianli Zhuo 1
Eren Kursun 1
Siobhán Clarke 1
Hongting Lin 1
Padmaraj Singh 1
Trongyen Lee 1
Moonjung Chung 1
Wolfgang Rosenstiel 1
ThuydM Le 1
François Boyer 1
Jeroen Voeten 1
João Marques-Silva 1
TaiHung Liu 1
Chauchin Su 1
Chidamber Kulkarni 1
Abhijit Chatterjee 1
Tim Kong 1
Andy Yan 1
Ra'ed Al-Dujaily 1
Raid Ayoub 1
Jason Tong 1
V Nair 1
Weikai Cheng 1
Charalambos Ioannides 1
Steven Derrien 1
Fang Gong 1
Sehwan Kim 1
Jinjun Xiong 1
Peiyu Huang 1
Xijiang Lin 1
Jie Gong 1
Les Walczowski 1
Dilvan Moreira 1
Venkat Thanvantri 1
Ashok Sudarsanam 1
Andrew DeOrio 1
Antara Ain 1
Shangping Ren 1
J Van Eijnhoven 1
Alex Doboli 1
Hai Lin 1
Chungki Oh 1
Jingqing Mu 1
Mengchen Wu 1
Richard Brown 1
Kiseok Chung 1
Erik D'Hollander 1
Michel Renovell 1
Xingguang Feng 1
Yiran Chen 1
Dongwoo Lee 1
Jonghee Yoon 1
Ahmed Abousamra 1
Dirk Niggemeyer 1
Pu Liu 1
Bilge Akgul 1
Tsuangwei Chang 1
Gregory Dimitroulakos 1
Hyunggyu Lee 1
Janet Wang 1
Alexandro Baldassin 1
James Moscola 1
Young Cho 1
Sudarshan Srinivasan 1
Jaehyun Park 1
Concepcion Sanz 1
Sotirios Xydis 1
George Economakos 1
Nicholas Imbriglia 1
Giovanni De Micheli 1
Sherief Reda 1
Takeshi Yamamoto 1
Satoshi Nakano 1
John Lee 1
Rajarshi Mukherjee 1
Martha Pollack 1
Rupak Majumdar 1
Samson Melamed 1
Nikhil Jayakumar 1
Thomas Parnell 1
Giacomo Marchetti 1
Sudipta Bhawmik 1
Ahmad Al-Yamani 1
Koen Van Eijk 1
Qin Zhao 1
Yentai Lai 1
Michele Malgeri 1
Maciej Ciesielski 1
Kumar Lalgudi 1
Marios Papaefthymiou 1
Songra Pan 1
Alan Hu 1
Xiaowei Li 1
Graeme Gange 1
Cristiana Bolchini 1
Juergen Schloeffel 1
Sandip Das 1
Ganesh Gopalakrishnan 1
LiehMing Wu 1
Chuanjun Zhang 1
Alexios Birbas 1
Bita Gorjiara 1
Nader Bagherzadeh 1
Mark Johnson 1
Dmitri Maslov 1
Gang Chen 1
Yaping Lin 1
Lu Sha 1
Mottaqiallah Taouil 1
Gang Chen 1
Reinhardt Euler 1
Yuzhen Niu 1
Bo Yao 1
Pingqiang Zhou 1
James Hoe 1
Bradley Carlson 1
Venkataramanan Balakrishnan 1
Shenghua Liu 1
Daniel Kroening 1
Carlos Fernández 1
Chris Bleakley 1
Bo Wang 1
Wonyong Sung 1
Mehrdad Majzoobi 1
Amit Agarwal 1
Chunan Chen 1
Duo Li 1
Michael Gester 1
Baoxian Zhao 1
Seungwon Kim 1
Taemin Lee 1
Hyunsun Park 1
Junwhan Ahn 1
Sparsh Mittal 1
Garng Huang 1
Farshad Firouzi 1
Tian Zhang 1
Savithri Sundareswaran 1
Fahimeh Jafari 1
Hasan Arslan 1
Haibo Wang 1
Jimson Mathew 1
Alokika Dash 1
Frédéric Vivien 1
Paul Chau 1
Swarup Bhunia 1
Prasun Ghosal 1
Myungsun Kim 1
Hyojung Lee 1
Sarmishtha Ghoshal 1
Yan Jia 1
Chungwei Lin 1
Ankit More 1
Adam Teman 1
Pascal Meinerzhagen 1
Swaminathan Narayanaswamy 1
Ramprasath S 1
Yichung Chen 1
Wei Zhang 1
Robert Johnson 1
Joachim Falk 1
Stefan Gheorghita 1
Andreas Hansson 1
Prasenjit Basu 1
Chengan Chien 1
Sounil Biswas 1
Chiaheng Tu 1
Gustavo Tellez 1
Seongseok Seo 1
Rafael Moreno 1
Philipp Mundhenk 1
Jingweijia Tan 1
Daler Rakhmatov 1
Mirko Loghi 1
Vijay D'Silva 1
Sri Parameswaran 1
Younghwan Park 1
Xrysovalantis Kavousianos 1
Subhas Nandy 1
Kazuhisa Ishizaka 1
Joanna Ho 1
Richard Wong 1
Avi Ziv 1
Jos Hulzink 1
Sezer Gören 1
F Ferguson 1
Dian Zhou 1
John Emmert 1
Jinian Bian 1
Haikun Zhu 1
Tomvander Aa 1
ShihCheng Tsai 1
Yongjin Ahn 1
Michael Kishinevsky 1
Siddharth Jain 1
Jean Rolt 1
Scott Chilstedt 1
Jinho Lee 1
Rohit Ramanujam 1
Bill Lin 1
Manoj Sachdev 1
Adit Singh 1
Turker Kuyel 1
Gustavo Neuberger 1
Lakshmi Chakrapani 1
Angchih Hsieh 1
Olinto Furtado 1
Tim Tuan 1
Yongsoo Joo 1
Donghwa Shin 1
Moritz Schmid 1
Sandip Kundu 1
Ryan Cochran 1
Atsuto Hanami 1
Juyueh Lee 1
Weifeng He 1
Juan Clemente 1
Kuolin Peng 1
Denis Flandre 1
Steven Nowick 1
Renyuan Zhang 1
Gary Tressler 1
Hyungjun Kim 1
Arseniy Vitkovskiy 1
Hamid Sarbazi-Azad 1
Changho Choi 1
Brentbyunghoon Kang 1
Steffen Peter 1
Zainalabedin Navabi 1
David Berner 1
Calin Ciordas 1
Stefan Pees 1
Heinrich Meyr 1
Hui Huang 1
Giuseppe Mangioni 1
Luc Bianco 1
Pradip Jha 1
Gang Chen 1
Werner Geurts 1
Johan Van Praet 1
Eduardo Pacheco 1
Hiroaki Suzuki 1
Tadao Yamanaka 1
Haruyuki Ohkuma 1
Hamid Mahmoodi 1
Alex Kondratyev 1
Zhifang Li 1
Lihua Yue 1
Chengjuei Yu 1
YiHsin Wu 1
Arthur Yeh 1
Ruibing Lu 1
Etem Deniz 1
Kazutoshi Wakabayashi 1
Xuchu Hu 1
Chiennan Liu 1
Chiachun Tsai 1
J Ramanujam 1
Dipankar Sarkar 1
Ted Szymanski 1
Udo Kebschull 1
Soumendu Bhattacharya 1
Min Xie 1
Nizar Dahir 1
Terrence Mak 1
Jianhua Li 1
Liang Shi 1
Mitchell Thornton 1
Mario Leung 1
Ryan Rakib 1
Muhammad Pasha 1
Junxia Ma 1
Gianpiero Cabodi 1
Alan Su 1
YuHsin Kuo 1
Debapriya Chatterjee 1
Yiding Han 1
Praveen Murthy 1
Antonio Pérez 1
Jay Brockman 1
Jiunlang Huang 1
Bijan Alizadeh 1
Mohammed Khatib 1
AnPing Wang 1
Pai Chou 1
Miron Abramovici 1
Ingrid Verbauwhede 1
Robert Rinker 1
Ugur Sezer 1
Chunkai Wang 1
Chingyu Chin 1
Dejun Mu 1
Mohit Tiwari 1
Xueliang Li 1
Weiyu Tang 1
Pejman Lotfi-Kamran 1
Mohammad Hosseinabady 1
Robert Schreiber 1
Bren Mochocki 1
Meenakshi Kaul 1
Alex OrailoĞLu 1
Saraju Mohanty 1
James Geraci 1
Priyank Gupta 1
Seetal Potluri 1
A Trinadh 1
Sebastien Guillet 1
Éric Rutten 1
Jean Diguet 1
Steffen Schlueter 1
Rickard Ewetz 1
Ya Wang 1
Yue Zhao 1
Jingwei Lu 1
Chulhong Park 1
Qinke Wang 1
Sayantan Das 1
Michael Taylor 1
Yenchun Lin 1
SueHong Chow 1
Guoqing Chen 1
Liang Chen 1
Eddie Hung 1
David Hély 1
Yongpan Liu 1
Song Jin 1
Huawei Li 1
Karin Avnit 1
Sudeep Pasricha 1
Yuru Hong 1
Philippe Grosse 1
Yves Durand 1
Owen Farell 1
Waichung Tang 1
Tiansi Hu 1
Robert Dick 1
Jinjun Xiong 1
YongHwan Kim 1
David Blaauw 1
ChunDa Du 1
Miad Faezipour 1
ChoonYik Tang 1
D Van Campenhout 1
Trevor Mudge 1
Rick McGeer 1
Chunghsiang Lin 1
Byunghyun Lee 1
Ilia Polian 1
Ken Kennedy 1
Yuzheng Ding 1
Sharat Prasad 1
David Whalley 1
ChuangYi Chiu 1
Ingjer Huang 1
Bruno Lavigueur 1
Zhihua Zhou 1
Dennis Huang 1
Chungkuan Cheng 1
Dong Lee 1
Geert Deconinck 1
Hsueh Lu 1
Nobuhiro Tsuda 1
Arijit Ghosh 1
C Krishna 1
Donatella Sciuto 1
Yi Zou 1
Kaijie Wu 1
Wennai Cheng 1
Xuan Guan 1
Guoqiang Chen 1
Waseem Ahmed 1
Yunchih Chang 1
Michael Glaß 1
Zhiying Wang 1
Jieun Lim 1
Nagesh Lakshminarayana 1
Bernd Becker 1
Kamyiu Lam 1
Chiawei Lee 1
Bailey Miller 1
Brian Tagiku 1
Sanghyeon Baeg 1
Weitsun Sun 1
Kunhyuk Kang 1
Jason Cheatham 1
Mauricio Ayala-Rincón 1
Hannahhonghua Yang 1
Qiang Zhou 1
Paul Pop 1
Traian Pop 1
Petru Eles 1
Swanwa Liao 1
Gunar Schirner 1
Andreas Gerstlauer 1
Xue Liu 1
Somnath Paul 1
Yuan Cai 1
Sungkyu Lim 1
Ricardo Reis 1
Chincheng Kuo 1
Éamonn Linehan 1
Chandan Karfa 1
Stefan Obenaus 1
Xiaojian Yang 1
Naran Sirisantana 1
Alex Yakovlev 1
Yinlong Xu 1
Fabrizio Lombardi 1
Christoph Kern 1
Zhaoliang Pan 1
Wei Zhao 1
Sreejit Chakravarty 1
Hungyi Li 1
Vladimir Zolotov 1
Stefano Quer 1
Henrik Esbensen 1
Li Shang 1
Zhuo Feng 1
Maria García 1
Marc Heijligers 1
Weitong Chuang 1
Einar Aas 1
Sagar Sabade 1
Xiaoping Tang 1
Jaehwanjohn Lee 1
Santiago Rodríguez 1
Subhankar Mukherjee 1
Pallab Dasgupta 1

Affiliation Paper Counts
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
Macau University of Science and Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
Huawei Technologies Co., Ltd. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
North China Electric Power University 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Microsoft Research 1
University of Potsdam 1
Beijing University of Chemical Technology 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of Central Florida 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Lancaster University 1
Oak Ridge National Laboratory 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers University 1
Nortel Networks 1
Institute of Computing Technology Chinese Academy of Sciences 1
Curtin University of Technology, Perth 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Gonzaga University 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
Lebanese American University 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Texas at San Antonio 1
University of Manchester 1
Universite de Bretagne-Sud 1
China National Petroleum Corporation 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
University of Kansas 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
University of Kaiserslautern 1
Nanjing University of Science and Technology 1
University of Kent 1
Auburn University 1
Oakland University 1
INRIA Rhone-Alpes 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Kwangwoon University 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Chengdu University of Information Technology 1
Washington State University Tri-Cities 1
National Taipei University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
Advanced Micro Devices, Inc. 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
East China Normal University 1
Villanova University 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Bar-Ilan University 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
University of Houston 2
Universitat Politecnica de Catalunya 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
Silesian Polytechnic University, Gliwice 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Indian Institute of Technology, Guwahati 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
Michigan Technological University 2
University of Tubingen 2
Southern Methodist University 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Alcatel-Lucent 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institute for Research in IT and Random Systems 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
Indian Institute of Technology Roorkee 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
New York University Abu Dhabi 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Korea University 3
Bogazici University 3
Delft University of Technology 3
Kitakyushu University 3
The University of Hong Kong 3
Hong Kong University of Science and Technology 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
RWTH Aachen University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
New York University 3
Portland State University 3
Hanyang University 3
University of Brasilia 3
Stony Brook University 3
University of Melbourne 3
University of Pisa 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
Hunan University 3
University of Seville 3
University of Cyprus 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
University of Electronic Science and Technology of China 4
Louisiana State University 4
Chung Hua University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Peking University 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
Swiss Federal Institute of Technology, Zurich 4
Microsoft 4
IBM Austin Research Laboratory 4
University of Milan 4
Syracuse University 4
Universite de Rennes 1 4
Pohang University of Science and Technology 4
University of Dortmund 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
Western Michigan University 5
Royal Institute of Technology 5
University of Calgary 5
Instituto Superior Tecnico 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
National University of Singapore 5
University of Bristol 5
University of North Texas 5
Agilent Technologies 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Indian Institute of Technology, Delhi 5
Nanjing University 5
Fujitsu America, Inc. 5
Universite Grenoble Alpes 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
Zhejiang University 6
North Carolina State University 6
University of Illinois 6
Fudan University 6
Brown University 6
University of California, Davis 6
Holst Centre 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
National Taiwan University of Science and Technology 6
Swiss Federal Institute of Technology, Lausanne 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
Universidade de Lisboa 6
University of Minnesota System 7
Linkoping University 7
HP Labs 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
University of California, Santa Cruz 7
Shanghai Jiaotong University 7
State University of Campinas 7
Utah State University 7
University of Wisconsin Madison 7
McGill University 8
Iowa State University 8
Nanyang Technological University 8
Northwestern University 8
Federal University of Santa Catarina 8
University of Science and Technology of China 8
Technical University of Munich 8
Indian Statistical Institute, Kolkata 8
University of Utah 8
Indian Institute of Technology, Madras 8
University of Bologna 8
Southern Illinois University at Carbondale 8
Karlsruhe Institute of Technology 8
Ulsan National Institute of Science and Technology 8
University of Michigan 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
University of Waterloo 9
Drexel University 9
Fuzhou University 9
Freescale Semiconductor 9
University of Connecticut 9
National Central University Taiwan 9
University of Freiburg 9
University of Illinois at Chicago 9
The University of British Columbia 10
Yuan Ze University 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
National University of Defense Technology China 10
Broadcom Corporation 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
Chung Yuan Christian University 10
NEC Corporation 10
Princeton University 11
University of Massachusetts Amherst 11
Imperial College London 11
University of Notre Dame 11
University of Tehran 11
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
University of Florida 12
Academia Sinica Taiwan 12
Korea Advanced Institute of Science & Technology 12
Samsung Electronics 13
University of Texas at Dallas 13
University of Patras 13
University of South Florida Tampa 14
Catholic University of Leuven 14
Complutense University of Madrid 14
National Chung Cheng University 15
University of California, Berkeley 15
University of Southern California 15
University of Erlangen-Nuremberg 16
Chinese Academy of Sciences 16
University of Arizona 17
Pennsylvania State University 18
IBM 18
Cadence Design Systems 18
Ghent University 18
Virginia Tech 19
Arizona State University 20
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
University of California, Santa Barbara 21
Tsinghua University 24
National Cheng Kung University 25
University of Maryland 26
Eindhoven University of Technology 26
Chinese University of Hong Kong 28
Synopsys Incorporated 28
Duke University 30
Intel Corporation 30
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
University of Texas at Austin 35
Purdue University 36
University of Pittsburgh 37
National Taiwan University 40
Carnegie Mellon University 40
University of California, Riverside 43
University of California, San Diego 43
National Chiao Tung University Taiwan 44
Indian Institute of Technology, Kharagpur 45
Texas A and M University 50
University of California, Irvine 63
National Tsing Hua University 65
University of California, Los Angeles 65
Seoul National University 67

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Volume 21 Issue 4, June 2016  Issue-in-Progress
Volume 22 Issue 1, May 2016  Issue-in-Progress
Volume 21 Issue 3, May 2016  Issue-in-Progress
Volume 21 Issue 2, January 2016

Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
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Volume 20 Issue 1, November 2014
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Volume 19 Issue 1, December 2013
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Volume 18 Issue 3, July 2013
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Volume 16 Issue 4, October 2011
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Volume 16 Issue 1, November 2010
Volume 15 Issue 4, September 2010
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Volume 15 Issue 1, December 2009
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