ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications

Developing circuits for streaming applications written in C (or its variants) can benefit greatly... (more)

Auxiliary Variables in Temporal Specifications

Assertion-based verification (ABV) for IP blocks given as synchronous RTL (register transfer level) descriptions has now widely gained acceptance. The challenge addressed here is ABV for systems on chip (SoC) modeled at the system level in SystemC TLM (Transactional Level Modeling). Requirements to be verified at this level of abstraction usually... (more)

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs

Due to the inappropriate assignment of bump pads or the improper assignment of I/O buffers, the constructed buffered I/O signals in an area-I/O... (more)

Array Size Computation under Uniform Overlapping and Irregular Accesses

The size required to store an array is crucial for an embedded system, as it affects the memory size, the energy per memory access, and the overall... (more)

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM

Multi-level cell (MLC) phase change RAM (PRAM) is expected to offer lower cost main memory than DRAM. However, poor write performance is one of the... (more)

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

3D technology for networks-on-chip (NOCs) becomes attractive. It is important to present an effective scheme for 3D stacked NOC router and... (more)

Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction

A digital microfluidic biochip (DMFB) is an attractive technology platform for revolutionizing... (more)

Parallel Power Grid Analysis Based on Enlarged Partitions

As the size and complexity of current VLSI circuits grows, faster power grid simulation is becoming more and more desirable. In this article, we... (more)

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands

Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy... (more)

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions

In this article, we investigate the application of different techniques for mitigating the impact of... (more)


As technology scales, thermal management for multicore architectures becomes a critical challenge due to increasing power density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core configurations. In multicore era, a chip-wide power budget, however, is not sufficient to ensure... (more)

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis

Soft error is nowadays a major reliability issue for nanoscale VLSI, and addressing it during high-level synthesis is essential to improve the... (more)


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ACM TODAES Special Section Call for Papers - IDEA: Integrating Dataflow, Embedded computing, and Architecture (Deadline is extended: Fab. 7
- Special Section Guest Editors: Twan Basten (Eindhoven University of Technology), Orlando Moreira (Intel), Robert de Groote (Twente University) 
- Contact:

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

Best Paper Award: Congratulations to Peter Milder, Franz Franchetti, James C. Hoe, and Markus Puschel on receiving the 2014 ACM TODAES Best Paper Award for their article titled Computer Generation of Hardware for Linear Digital Signal Processing Transforms, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 2, Article 15, April 2012.

Forthcoming Articles
Statistical Rare Event Analysis and Parameter Guidance by Elite Learning Sample Selection

Accurately estimating the failure region of rare events for memory-cell and analog circuit blocks under process variations is a challenging task. In this article, we propose a new statistical method, called EliteScope to estimate the circuit failure rates in rare event regions and to provide conditions of parameters to achieve targeted performance. The new method is based on the iterative blockage framework to reduce the number of samples. But it consists of two new techniques to improve existing methods. First, the new approach employs an elite learning sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the EliteScope identifies the failure regions in terms of parameter spaces to provide a good design guidance to accomplish the performance target. It applies variance based feature selection to find the dominant parameters and then determine the in-spec boundaries of those parameters.We demonstrate the advantage of our proposed method using several memory and analog circuits with different number of process parameters.Experiments on four circuit examples show that it EliteScope achieves a significant improvement on failure region estimation in terms of accuracy and simulation cost over traditional approaches.The 16-bit 6T-SRAM column example also demonstrate that the new method is scalable for handling large problems with large number of process variables.

EBL Overlapping aware Stencil Planning for MCC System

Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters) can be printed in one shot. Recently the traditional EBL system is extended into multi-column cell (MCC) system to further improve the throughput. In MCC system, several independent CPs are used to further speed-up the writing process. Because of the area constraint of stencil, MCC system needs to be packed/planned carefully to take advantage of the characters. In this paper, we prove that the overlapping aware stencil planning (OSP) problem is NP-hard. Then we propose E-BLOW, a tool to solve MCC system OSP problem. E-BLOW involves several novel speedup techniques, such as successive relaxation and dynamic programming. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system.

Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study

Phase-change memory (PCM) has several benefits including low cost, non-volatility, byte-addressability, etc., and limitations such as write endurance. There have been several hardware approaches to exploit the benefits while minimizing the negative impact of limitations. Software approaches could give further improvements, when used together with hardware approaches, by taking advantage of write behavior present in the program, e.g., write behavior on dynamically allocated data, which is hardly captured by hardware approaches. This work proposes a software design methodology to reduce costly PCM writes. First, on top of existing hardware approach such as Flip-N-Write, we advocate exploiting the capability of PCM bit-level differential write in the software by judiciously reusing previously allocated memory resource. In order to avoid wear-out incurred by the reuse, we present software-based wear-leveling methods which distribute writes across PCM cells. In order to further reduce PCM writes, we propose identifying data whose loss does not affect the functionality of the underlying software, and then diverting write traffic for those data items to volatile memory. To evaluate the effectiveness of these methods, as a case study, we applied the proposed methods to the design of journaling in SQLite which is an important database application commonly used in smartphones. For the experiments, we used an in-house PCM-based prototype board. Our experiments with four representative mobile applications show that the proposed design methods, which is applied on top of the hardware approach, Flip-N-Write, result in 75.2% further reduction in total bit updates in PCM, on average, without aggravating wear out compared with the baseline of PCM-based journaling which is based only on the hardware approach. Also, the proposed design methods result in 58.3% reduction in energy consumption and 31.7% reduction in runtime compared to the baseline design of SQLite journaling on Flash memory.

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, e.g., in 14nm and below, where double patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches such as M2 and M3. Self-aligned double patterning (SADP) provides better control on the line edge roughness and overlay but it has very restrictive design constraints and prefers regular layout patterns. This paper presents a comprehensive pin access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include pre-computation of both intra-cell and inter-cell pin accessibility, as well as local and global pin access planning to enable the handshaking between standard cell level pin access and detailed routing under SADP constraints. Pin access driven rip- up and re-route scheme is further proposed to improve the ultimate routability. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology node independent design methodology for these rail clamp circuits that takes process, voltage, and temperature variations into consideration. The methodology can be used as a cookbook by the designer or be used to automate the entire design process. Tradeoffs between various design metrics such as esd performance (Human Body Model), leakage, and area are considered. Simplified circuit models for the rail clamp are presented to gain insights into its working and to size the circuit components. A rail clamp for core power domain is designed using the proposed approach in 40 nm low power process and performance results of the design are also presented. The effectiveness of the design methodology is proven by comparing the obtained design with the best design from among 250,000 designs obtained by randomly sampling from the design space.

Power, Area, and Performance Optimization of Standard Cell Memory Arrays through Controlled Placement

Standard cell memories (SCMs) are an alternative to foundry provided SRAM macros that can be defined, synthesized and placed and routed as part of the digital design flow, providing design flexibility, energy efficiency, low-voltage operation, and area efficiency for small memories. However, implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array. In this paper, we present a design methodology for optimizing the physical implementation of SCMs, as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, non-congested layout with high utilization, resulting in reduced area, wire-length, and power consumption. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a 28nm FD-SOI technology, and compared with non-controlled SCMs, as well as with SRAM macros. The controlled SCMs provide an average 25% reduction in area, as compared to non-controlled implementations. Power and performance comparisons of controlled SCM blocks of a commonly found 256X32 (1kbyte) memory with foundry provided SRAMs show over 65% and 10% reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC based test-chip, providing more than 50% power reduction, as compared to equivalently sized compiled SRAMs under a benchmark application.

Accurate Modeling of Nonideal Low Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit Averaging Techniques

The development of enhanced modeling techniques for the simulation of switched-mode Pulse Width Modulated (PWM) DC-DC power converters using circuit averaging is the main focus of this paper. The circuit averaging technique has traditionally been used to model the behavior of PWM DC-DC converters without considering important nonideal characteristics of the switching devices. As a result, most of these existing approaches present simplified models that are ideal or linearized, and do not accurately account for the performance characteristics of the converter. This is especially problematic for low-power applications. In this paper, we present an enhanced nonideal behavioral circuit averaged model that makes the simulation of DC-DC converters both computationally efficient and accurate, thereby presenting an important tool for circuit designers. Experimentally, we show that our Verilog-A based new model allows for accurate simulation of both Buck and Boost type PWM converters operating in either CCM or DCM modes while providing more than one order of magnitude speedup over the transistor-level simulation.

Performance Evaluation of NoC-based Multicore Systems: From Traffic Analysis to NoC Latency Modelling

In this survey, we review several mathematical approaches for performance evaluation of NoC-based multicore systems, starting from the traffic analysis to the complex NoC models for latency evaluation. Towards this end, we first summarize the NoC workload to capture the application traffic characteristics. Specifically, we focus on techniques of non-Poisson and fractal (i.e., self-similar or long range memory dependent) traffic models and their impacts on the multicore platform design. Then, we review the analytical techniques for evaluating the performance of an NoC under the given input traffic. We investigate NoC analytical models for average as well as maximum latency predictions. Another interesting research direction in NoC performance evaluation consists of combining simulation and analytical models in order to exploit their advantages together. Towards this end, we discuss several newly proposed approaches that use hardware-based or learning-based techniques.

On Battery Recovery Effect in Wireless Sensor Nodes

With the perennial demand for longer runtime of battery-powered Wireless Sensor Nodes (WSNs), several techniques have been proposed to increase the battery runtime. One such class of techniques exploiting the battery recovery effect phenomenon claims that performing an intermittent discharge instead of a continuous discharge will increase the usable battery capacity. Several works in the areas of embedded systems and wireless sensor networks have assumed the existence of this recovery effect and proposed different power management techniques in the form of power supply architectures (multiple battery setup) and communication protocols (burst mode transmission) in order to exploit it. However, until now, a systematic experimental evaluation of the recovery effect has not been performed with real battery cells, using high accuracy battery testers to confirm the existence of this recovery phenomenon. In this paper, a systematic evaluation procedure is developed to verify the existence of this battery recovery effect. Our experimental results do not show any evidence of this recovery effect, and in particular, our results show a significant deviation from the stochastic battery models which were used by many power management techniques. Therefore, the existing power management approaches that rely on this recovery effect do not hold in practice. Instead of a battery recovery effect, our experimental results show the existence of the rate capacity effect, which is the reduction of usable battery capacity with higher discharge power, to be the dominant electrochemical phenomenon that should be considered for maximizing the runtime of WSN applications. We outline power management techniques that minimize the rate capacity effect in order to obtain a higher energy output from the battery.

A Survey Of Techniques for Cache Locking

Cache memory, although important for boosting application performance, is also a source of execution time variability, which makes its use difficult in systems requiring WCET (worst case execution time) guarantees. Cache locking (CL) is a promising approach for simplifying WCET estimation and providing predictability and hence, several commercial processors provide ability for locking cache. However, CL also has its disadvantages (e.g. extra misses for unlocked blocks, complex algorithms required for selection of locking contents) and hence, a careful management is required to realize the full potential of CL. In this paper, we present a survey of techniques proposed for cache locking. We categorize the techniques in several groups to underscore their similarities and differences. We also discuss the opportunities and obstacles in using CL. We hope that this paper will help researchers in getting insights into CL schemes and will also stimulate further work in this area.

Streaming Sorting Networks

Clock-Tree-Aware Incremental Timing-Driven Placement

The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step towards timing closure. Current TDP techniques improve critical paths but overlook the impact of register placement on clock tree quality. On the other hand, register placement techniques found in the literature mainly focus on power consumption, disregarding timing and routabilty. Indeed, postponing register placement may undermine the optimization achieved by TDP, since the wiring between sequential and combinational elements would be touched. This work proposes a new approach for an effective coupling between register placement and TDP that relies on two key aspects to handle sequential and combinational elements separately: only the registers in the critical paths are touched by TDP (in practice they represent a small percentage of the total number of registers), and the shortening of clock tree wirelength can be obtained with limited variation in signal wirelength and placement density. The approach consists of two steps: 1) incremental register placement guided by a virtual clock tree to reduce clock wiring capacitance while preserving routability in terms of signal wirelength and density, 2) incremental TDP to minimize the total negative slack. For the first step, we propose a novel technique that combines clock-net contraction and register clustering forces to reduce the clock wirelength. For the second step, we adopted the Lagrangian Relaxation formulation that was proposed in our previous work to minimize total negative slack for both setup and hold timing violations. We extend the solution technique through a new discrete search that employs the Euclidean distance to define a proper neighborhood. The experimental results showed the effectiveness of the proposed approach in terms of timing closure, clock-tree compactness and routability.

An Effective Chemical Mechanical Polishing Fill Insertion Approach

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This paper presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approachesFast Median approach , LP approach and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

Parasitic-aware Common-centroid FinFET Placement and Routing for Current-ratio Matching

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated circuit design due to more effective channel control and lower power consumption. However, the gate misalignment problem result- ing from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the Fin- FET technology to analog circuit design, the variation of drain currents can destroy the current-ratio matching among tran- sistors and degrade the circuit performance. In this paper, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

Synthesis of Dual-Mode Circuits through Library Design, Gate Sizing, and Clock Tree Optimization

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to minimize performance loss at NTV or maximize NTV-mode frequency. A standard cell library for dual-mode circuits is proposed; we balance transistor sizes and reduce stack transistors. Gate sizing is performed to minimize negative slacks at both modes; a new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV-mode frequency. Clock tree synthesis is re-formulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV-mode clock period is reduced by 24% on average; clock skew at NTV decreases by 13% on average.

Path Selection for Real-Time Communication on Priority-Aware NoCs

This work investigates selecting paths for communication flows when deploying a hard real-time application on a chip-multiprocessor system. This chip-multiprocessor system uses a priority-aware real-time network-on-chip interconnect between the processors. Given a mapping of the computation tasks onto the chip-multiprocessor, the problem we address in this work is to discover paths the communication flows take such that hard real-time deadlines of flows are met. Furthermore, we must ensure that deadlines are met even in the presence of direct and indirect interference from other flows sharing network links on the path. To achieve this, our algorithm utilizes a stage-level analysis for real-time communication to determine the impact of a network link being used by a flow, and its effect on other flows sharing the link. The path selection algorithm uses heuristics such as selecting links with least interference, and considering lower priority flows when dedicating links to paths of higher priority flows since an optimal one is intractable. The algorithm also considers constraints on the number of virtual channels at each router port in the network. The statistically significant experimental results show an improvement in schedulability by 5% and 12% over existing path selection algorithms such as Minimum Interference Routing and Widest Shortest Path algorithms, respectively. We also present a set-top box case study to further illustrate the benefits of using the proposed algorithm.

FH-OAOS: A Fast 4-step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction

With the sharply increase of very large scale integrated (VLSI) circuit density, we are faced with many knotty issues. Particularly in the routing phase of VLSI physical design, the interconnection effects directly relate to the final performance of circuits. However, the optimization capability of traditional rectilinear architecture is limited, thus both academia and industry have been devoted to non-rectilinear architecture in recent years, especially octilinear architecture which is the most promising one because it can greatly improve the performance of modern chips. In this article, we design OAGROA, an obstacle-avoiding global router in octilinear architecture, by constructing an obstacle-avoiding octilinear Steiner minimal tree (OAOSMT). Our approach first constructs an obstacle-free Euclidean minimal spanning tree (OFEMST) on the given pins based on Delaunay triangulation (DT). Then, two lookup tables about OFEMSTs edge are generated, which can be seen as the information center of OAGROA, and can provide information support for router operation. Next, an efficient obstacle-avoiding strategy is proposed to convert the OFEMST into an obstacle-avoiding octilinear Steiner tree (OAOST). Finally, the generated OAOST is refined to construct the final OAOSMT by applying three effective strategies. Experimental results on various benchmarks show that OAGROR achieves 61.97 times speedup on average, while the average wirelength of final OAOSMT is only 0.36% larger than the best existing solution.

Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling

Multicore platforms are increasingly used in real-time embedded applications. In the development of such applications, an efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and allowing savings in stack space. In this paper, we address the problem of mapping tasks to cores and assignment of the scheduling parameters for both partitioned Fixed-Priority and EDF scheduling algorithms with PTS. We formulate the optimization problems using Mixed Integer Linear Programming framework, and present a Simulated Annealing algorithm as well as an efficient heuristic algorithm as practical alternatives. We perform extensive performance evaluations using random synthetic tasksets and industrial case studies.

A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition using Wearables (post conference paper)

Wearables are being widely utilized in health and wellness applications, primarily due to the recent advances in the sensor and wireless communication, which enhance the promise of wearable systems in providing continuous and real-time monitoring and interventions. Wearables are generally composed of hardware/software components for collection, processing, and communication of physiological data. Practical implementation of wearable monitoring in real-life applications is currently limited due to notable obstacles. The wearability and form factor are dominated by the amount of energy needed for sensing, processing and communication. In this paper, we propose an ultra low-power granular decision making architecture, also called screening classifier, which can be viewed as a tiered wake up circuitry, consuming three orders of magnitude less power than the state-of-the-art low-power microcontrollers. This processing model operates based on computationally simple template matching modules, which is ideally performed with low sensitivity but operates at low power. Initial template matching rejects signals that are clearly not of interest from the signal processing chain keeping the rest of processing blocks idle. If the signal is likely of interest, the sensitivity and the power of the template matching modules are gradually increased and ultimately the main processing unit is activated. We pose optimization techniques to efficiently split a full template into smaller bins, called mini-templates, and activate only a subset of bins during each classification decision. Our experimental results on real data show that this signal screening model reduces power consumption of the processing architecture by a factor of 70% while the sensitivity of detection remains at least 80%.

Construction of Reconfigurable Clock Trees for MCMM Designs using Mode Separation and Scenario Compression

The clock networks of many modern circuits have to operate in multiple corners and multiple modes (MCMM). We propose to construct mode-reconfigurable clock trees (MRCTs) based on mode separation and scenario compression. The technique of scenario compression is proposed to consider the timing constraints in multiple scenarios at the same time, compressing the MCMM problem into an equivalent single-corner multiple-mode (SCMM), or single-corner single-mode (SCSM) problem. The compression is performed by combining the skew constraints of the different scenarios in skew constraint graphs based on delay linearization and dominating skew constraints. An MRCT consists of several clock trees and mode separation involves, depending on the active mode, selecting one of the clock trees to deliver the clock signal. To limit the overhead, the bottom part (closer to the clock sinks) of all the different clock trees are shared and only the top part (closer to the clock source) of the clock network is mode reconfigurable. The reconfigurable is realized using OR-gates and an one-input-multiple-output demultiplexer. The experimental results show that for a set of synthesized MCMM circuits, with 715 to 13, 216 sequential elements, the proposed approach can achieve high yield.

Floorplanning and Topology Synthesis for Application Specific Network-on-Chips with RF-Interconnect

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on chip communication becomes more and more complex and the power consumption imposes the major challenge for designing ASNoCs. In this paper, we first time propose a four-stage floorplanning and topology synthesis approach for ASNoCs with Radio Frequency Interconnect (RF-I). Firstly, considering the advantage of RF-I in long distance on-chip communication, we integrate the floorplanning and clustering to explore the optimal clustering of cores, where the cores belonging to the same cluster will share the same switch for communications, form an island, and occupy a contiguous physical region. After the switches and network interfaces are inserted into the floorplan, the allocation of routing paths and the RF-I logical channels are integrated in an iterative procedure to generate fine-grain dynamically reconfigurable ASNoC topologies. Finally, considering the signal integrity of RF-I, we adjust the placement of the switches by a simulated annealing-based method to reduce the number of the RF-I routing corners. To evaluate the placement of switches, we propose a dynamical programming based method to route the transmission line and count the routing corners in linear time. The results show that, using RF-I, we can reduce the power consumption of ASNoCs by 20%-29%.

DC Characteristics and Variability on 90nm CMOS Transistor Array-style Analog Layout

In MOS analog layout, the variability suppression is becoming a major issue as well as the layout efficiency. Introducing a transistor array(TA)-style to analog layout, this paper addresses the layout-dependent variability based on the measurement results of test chips on 90nmCMOS process. In TA-style, a large transistor is decomposed into a set of unified sub-transistors are connected in series or parallel. Focusing one row layout of diffusion-sharing for the multiple gates, we analyze the current direction dependent variability and the leakage current via off-gates for the electrical isolation. Furthermore, we present several analog design cases on TA including analysis of the impact on the DC characteristics caused by the transistor channel decomposition.


Publication Years 1996-2016
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First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Fellows (2013)
ACM Distinguished Member (2008)
ACM Senior Member (2006)
Jason Cong ACM Fellows (2008)
Giovanni DeMicheli ACM Fellows (2001)
Srinivas Devadas ACM Fellows (2014)
Nikil D. Dutt ACM Fellows (2014)
ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
W. Kent Fuchs ACM Fellows (2000)
Soheil Ghiasi ACM Senior Member (2015)
Ronald L. Graham ACM Fellows (1999)
Rajiv Gupta ACM Fellows (2009)
Matthew Guthaus ACM Senior Member (2013)
John P Hayes ACM Fellows (2001)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
ACM Fellows (1996)
Andrew Kahng ACM Fellows (2012)
Sung Mo Kang ACM Fellows (2001)
Kenneth W Kennedy ACM Fellows (1995)
Tei-Wei Kuo ACM Fellows (2015)
John Lee ACM Senior Member (2014)
Sharad Malik ACM Fellows (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM - IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Krishna Palem ACM Fellows (2005)
Ian Parberry ACM Distinguished Member (2015)
Janak H Patel ACM Fellows (2001)
Massoud Pedram ACM Distinguished Member (2008)
Martha Pollack ACM Fellows (2011)
Dhiraj Pradhan ACM Fellows (1999)
Viktor Prasanna ACM Fellows (2007)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM - IEEE CS Eckert-Mauchly Award (2002)
ACM Fellows (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
ACM Fellows (1996)
Karem Sakallah ACM Fellows (2012)
Alberto Luigi Sangiovanni Vincentelli ACM Fellows (2014)
Robert Schreiber ACM Fellows (2012)
ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Donald E Thomas ACM Fellows (2007)
Mateo Valero ACM Distinguished Service Award (2012)
ACM - IEEE CS Eckert-Mauchly Award (2007)
ACM Fellows (2002)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Marilyn Claire Wolf ACM Fellows (2001)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 16
Nikil Dutt 15
Jason Cong 12
Irith Pomeranz 11
Krishnendu Chakrabarty 11
Tingting Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
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Keven Dunn 1
Rajeshkumar Sambandam 1
Karthikeyan Lingasubramanian 1
Sandeep Gupta 1
Tobias Becker 1
Takayasu Sakurai 1
Xufa Wang 1
Jun Seomun 1
Subhashis Majumder 1
Jean Berge 1
Joan Lopez 1
ChungHwang Chen 1
Michel Boyer 1
Srikanth Venkataraman 1
Yahya Osais 1
JyhMou Tseng 1
Horácio Neto 1
Degang Chen 1
Joseph Shinnerl 1
Markus Seuring 1
Randall Geiger 1
Pinar Korkmaz 1
Qingan Li 1
Esteban Tlelo-Cuautle 1
Klaus Eckl 1
Kuenjong Lee 1
Tsungchu Huang 1
K Tsai 1
Yihuang Hung 1
Yeanyow Hwang 1
Sungwoo Hur 1
Ashok Jagannathan 1
Meihsiang Tsai 1
Ernest Kuh 1
Gilles Sicard 1
Yangdong Deng 1
Jennifer Dworak 1
Nuno Alves 1
Liang Shi 1
Yue Yu 1
Cornelis Van Eijk 1
Jürgen Teich 1
Rui Zheng 1
Jianhua Li 1
Harikumar Somakumar 1
Saeed Shamshiri 1
Jef Meerbergen 1
Eric Johnson 1
Hadi Esmaeilzadeh 1
Janusz Brzozowski 1
TungChieh Tsai 1
Sanghoon Kwak 1
Srikanth Chandrasekaran 1
John Backes 1
Marc Riedel 1
Vivek Joshi 1
Gagan Hasteer 1
Jing Zeng 1
P Bannerjee 1
Peter Bertels 1
Hsipin Ma 1
Bontae Koo 1
Bettina Braitling 1
Picheng Hsiu 1
Gang Qu 1
Qi Guo 1
Lokwon Kim 1
John Villasenor 1
Hamid Azad 1
Marjan Asadinia 1
Peter Middelhoek 1
Adam Kaplan 1
Amit Singh 1
Juan De Vicente 1
Chao Wang 1
Kyle Stegner 1
Andrew Wolfe 1
Yau Li 1
Paolo Camurati 1
Huankai Peng 1
HsuanMing Huang 1
Laurence Goodby 1
Shi Lin 1
Wanting Lo 1
Chiehjui Lee 1
Luís Guerra E Silva 1
Chandu Visweswariah 1
Raj Nadakuditi 1
Shashidhar Thakur 1
Adrian Ludwin 1
Vivek Sarin 1
Tiempo Sas 1
Yuhao Zhu 1
Kundan Nepal 1
Francesco Zanini 1
Colin Jones 1
Wenjong Fang 1
Naifeng Jing 1
Santiago Mok 1
Michael Hsiao 1
James Li 1
Vincent Mooney 1
David Bild 1
Gregory Bok 1
Gauthier Lafruit 1
Matthew Gately 1
Scott Little 1
Claudio Sansoè 1
Piet Engelke 1
Michael Mefenza 1
Hsiangpang Li 1
Jingwei Lu 1
Said Hamdioui 1
Adwait Gupte 1
Genggeng Liu 1
Wenzhong Guo 1
Sally McKee 1
Keshab Parhi 1
Kevin Lepak 1
Sudip Roy 1
Linzhang Wang 1
Namita Sharma 1
Gerda Janssens 1
Jongchul Lee 1
Zhonghai Lu 1
Jef Van Meerbergen 1
Rainer Leupers 1
Raminder Bajwa 1
Qubo Hu 1
Feng Liu 1
Krishnan Srinivasan 1
Vijaykumar Ramamurthi 1
Tanja Van Achteren 1
I Hsu 1
Menghuan Wu 1
Hasan Khalifeh 1
Plamen Nikolov 1
Yu Hu 1
Roberto Cordone 1
Michio Komoda 1
Zhen Chen 1
Shihhung Weng 1
Fang Liu 1
Sandro Rigo 1
Max Schultz 1
Ronny Krashinsky 1
Antonis Papanikolaou 1
Tomas Pecenka 1
Lukáš Sekanina 1
Zdeněk Kotásek 1
Alan Coppola 1
Chakchung Cheung 1
Wei Jiang 1
Yu Liu 1
Tomtong Jing 1
Robi Dutta 1
Sandip Ray 1
Jaideep Dastidar 1
David Lindberg 1
Kuanyu Lin 1
Shaz Qadeer 1
I Tseng 1
Chita Das 1
Bruno Rouzeyre 1
Nong Xiao 1
Jongeun Lee 1
Ralph Hasholzner 1
Stefan Hillebrecht 1
Jiantao Wang 1
Rami Melhem 1
Frank Vahid 1
Wenrui Gong 1
Brian DeRenzi 1
Nathan Denny 1
J Chen 1
Yan Lin 1
John Lockwood 1
Raymond Hoare 1
U Rovati 1
Ausif Mahmood 1
Sabyasachi Das 1
Krste Asanović 1
Huaizhi Wu 1
Sudarshan Bahukudumbi 1
William Hung 1
Sumit Gupta 1
Mohammed Elshoukry 1
Hongliang Chang 1
Stephen Cauley 1
Ying Hu 1
Yufu Zhang 1
Mohamed Elwakil 1
Seongook Jung 1
Chittaranjan Mandal 1
Stephen Edwards 1
Ali Pınar 1
Youtao Zhang 1
Zheng Xu 1
Hamid Shojaei 1
Giorgio Natale 1
Qiang Ma 1
Martin Wong 1
Yaolin Chang 1
Jackey Yan 1
Chris Chu 1
Yongwen Wang 1
Yongjoo Kim 1
Sanghyun Park 1
Matthias Sauer 1
Tobias Schubert 1
Dominik Erb 1
Minseok Kang 1
Baktash Boghrati 1
Hai Wang 1
Tim Nieberg 1
José Costa 1
Ying Tan 1
Jiajia Li 1
José Pineda De Gyvez 1
Domenic Forte 1
Ankur Srivastava 1
Martin Leucker 1
Renjie Lee 1
Wenpin Tu 1
Evangelos Eleftheriou 1
Thomas Griffin 1
Hakan Aydín 1
Seokhyeong Kang 1
Bradley Kiddie 1
Daniel Limbrick 1
Haibao Chen 1
Xin Huang 1
Ramin Bashizade 1
Youtao Zhang 1
Yoonseok Yang 1
Samarjit Chakraborty 1
Chrystian Guth 1
Hokyoon Lee 1
Florent De Lamotte 1
Sharad Sinha 1
Yentai Lai 1
Songra Pan 1
Dhiraj Pradhan 1
Chaowen Tzeng 1
Joachim Anlauf 1
Kueichung Chang 1
Jihsheng Shen 1
Sami Taktak 1
Jianli Zhuo 1
Xingguang Feng 1
Rupak Majumdar 1
Giacomo Marchetti 1
Samson Melamed 1
Nikhil Jayakumar 1
Rajarshi Mukherjee 1
Martha Pollack 1
Frederik Vandeputte 1
Stelios Mamagkakis 1
Justin Stander 1
Puneet Sharma 1
Yubin Zhang 1
Daujieu Yang 1
Huihsin Hsu 1
Jenhao Chen 1
Arnab Sinha 1
Bhaskar Pal 1
Thomas Mittelholzer 1
Charles Camp 1
Yang Zheng 1
Weijian Su 1
Ingoo Heo 1
Abhishek Koneru 1
Leila Delshadtehrani 1
Hamed Farbeh 1
Leandro Indrusiak 1
Osmar Dos Santos 1
Gwan Choi 1
Haotse Chen 1
Dacheng Juan 1
Diana Marculescu 1
Dip Goswami 1
Claudio Talarico 1
Waishing Luk 1
Ying Qin 1
Shengyu Shen 1
Huadong Dai 1
Qi Zhu 1
Gregor Goessler 1
Yehchi Chang 1
Wei Hu 1
Chia Yen 1
Robert Rinker 1
Hui Huang 1
Ingrid Verbauwhede 1
Ugur Sezer 1
Jimson Mathew 1
Alokika Dash 1
ShihCheng Tsai 1
Yongjin Ahn 1
Denis Flandre 1
Steven Nowick 1
Juan Clemente 1
Kuolin Peng 1
Christian Haubelt 1
Joachim Keinert 1
Mustafa Baz 1
Koen De Bosschere 1
Gayatri Mehta 1
Zhongyi Jin 1
Curt Schurgers 1
Qiang Xu 1
Kunal Ganeshpure 1
Liling Hung 1
Kuanhsien Ho 1
Yuanfang Hu 1
Adam Hartman 1
Douglas Keller 1
Jongkyung Paek 1
EnShou Chang 1
Viktor Lapinskii 1
Gustavo De Veciana 1
Ibrahim Hajj 1
Vikram Saxena 1
Francisco Fernández 1
Giovanni Squillero 1
Chihhung Liu 1
Syyen Kuo 1
Paul Feautrier 1
Xiaofang Wang 1
Hsien Lee 1
Filipa Duarte 1
Jun Zhou 1
Xinzhang Jia 1
Chen Li 1
Kuohua Wang 1
Ricardo Jacobi 1
Zuoyuan Li 1
Tero Rissa 1
Chris Bleakley 1
Hidehiro Takata 1
Yosinori Watanabe 1
Renshen Wang 1
Maciej Ciesielski 1
Marios Papaefthymiou 1
Michele Malgeri 1
Michael Münch 1
Kumar Lalgudi 1
Anshul Kumar 1
Swarup Das 1
Laurent Freund 1
J Lee 1
Franc Breglez 1
Giri Tiruvuri 1
Michael Gasteier 1
Ismed Hartanto 1
Kuangchien Chen 1
W Fuchs 1
Koen Danckaert 1
Noureddine Chabini 1
Steven Levitan 1
Dirk Niggemeyer 1
Katrina Lu 1
Kun Yuan 1
Dimitris Nikolos 1
Guilherme Ottoni 1
Min Zhao 1
Szuchi Wang 1
Shijie Wen 1
Jianchao Lu 1
Vijay Pitchumani 1
David Kidd 1
Scott Van Sooy 1
Ivan Hom 1
Gert Goossens 1
Dirk Lanneer 1
Joan Carletta 1
Mehrdad Nourani 1
Teemu Pitkänen 1
Hirofumi Shinohara 1
Luc Bianco 1
Pradip Jha 1
Giuseppe Mangioni 1
Miron Abramovici 1
Cécile Belleudy 1
Frédéric Rousseau 1
Zhanglei Wang 1
Marcus Schmitz 1
Bashir Al-Hashimi 1
Moonjung Chung 1
ThuydM Le 1
Trongyen Lee 1
Wolfgang Rosenstiel 1
François Boyer 1
Jeroen Voeten 1
Chauchin Su 1
João Marques-Silva 1
TaiHung Liu 1
Chidamber Kulkarni 1
Andy Yan 1
Manoj Sachdev 1
Adit Singh 1
Turker Kuyel 1
Gustavo Neuberger 1
Abhijit Chatterjee 1
Tim Kong 1
Lakshmi Chakrapani 1
Angchih Hsieh 1
Gregory Dimitroulakos 1
Bilge Akgul 1
Tsuangwei Chang 1
Hyunggyu Lee 1
Pu Liu 1
Angeliki Kritikakou 1
Hsiangyu Lu 1
Yiran Chen 1
Ulf Schlichtmann 1
Bernd Wurth 1
Olivier Sentieys 1
Frédéric Vivien 1
Paul Chau 1
Saket Gupta 1
Pai Chou 1
Sartaj Sahni 1
Anjur Krishnakumar 1
Jiang Hu 1
Vilasita Kuntamukkala 1
Sotirios Xydis 1
George Economakos 1
Nicholas Imbriglia 1
Giovanni De Micheli 1
Sherief Reda 1
Takeshi Yamamoto 1
Satoshi Nakano 1
John Lee 1
Nagu Dhanwada 1
Steve Tjiang 1
Ahmad Al-Yamani 1
Xiaoqing Wen 1
Andrew Cassidy 1
Hua Xiang 1
Arijit Mondal 1
Xiaoqing Yang 1
Yuliang Wu 1
Bert Geelen 1
Jaehyun Kim 1
Rajeev Rao 1
David Van Campenhout 1
Dinesh Ramanathan 1
Hussain Al-Asaad 1
Jonathan Martin 1
Rina Panigrahy 1
Christophe Bobda 1
Hungsheng Chang 1
Tianshi Chen 1
Ra'ed Al-Dujaily 1
Raid Ayoub 1
Jason Tong 1
Charalambos Ioannides 1
Fang Gong 1
V Nair 1
Weikai Cheng 1
Steven Derrien 1
Robert Schreiber 1
Alex OrailoĞLu 1
Peiyu Huang 1
Ashok Sudarsanam 1
Meenakshi Kaul 1
Sehwan Kim 1
Jinjun Xiong 1
Xijiang Lin 1
Venkat Thanvantri 1
Antara Ain 1
Dilvan Moreira 1
Jie Gong 1
Les Walczowski 1
Andrew DeOrio 1
Shangping Ren 1
J Van Eijnhoven 1
Sandip Kundu 1
Ryan Cochran 1
Moritz Schmid 1
Atsuto Hanami 1
Juyueh Lee 1
Weifeng He 1
David Berner 1
Calin Ciordas 1
Alex Doboli 1
Zainalabedin Navabi 1
Hai Lin 1
Chungki Oh 1
Jingqing Mu 1
Mengchen Wu 1
Richard Brown 1
Erik D'Hollander 1
Kiseok Chung 1
Juergen Schloeffel 1
Michel Renovell 1
Lu Sha 1
Yaping Lin 1
Mottaqiallah Taouil 1
Gang Chen 1
Reinhardt Euler 1
Olivier Temam 1
Depei Qian 1
Salvador Mir 1
Hao Li 1
Vijay Sundararajan 1
Juan Lanchares 1
Rajiv Gupta 1
Qiuping Yi 1
Zili Shao 1
Koen Van Eijk 1
Qin Zhao 1
E Mariatos 1
Hsinhung Lin 1
Janet Wang 1
James Moscola 1
Young Cho 1
Yoshiaki Fukui 1
Alexandro Baldassin 1
YannRue Lin 1
Sudarshan Srinivasan 1
Jaehyun Park 1
Concepcion Sanz 1
Yihlang Li 1
Mohamed Zahran 1
Douglas Myers 1
Mohammad Foroozannejad 1
Vijaykrishnan Narayanan 1
Hassan Salamy 1
Robert Brayton 1
Yiran Chen 1
Dongwoo Lee 1
Jonghee Yoon 1
Ahmed Abousamra 1
Jonghee Youn 1
Yuan Yuan 1
Christian Hochberger 1
Alexander Weiss 1
Christian Panten 1
Thomas Parnell 1
Dakai Zhu 1
Sudipta Bhawmik 1
Petru Eles 1
Yoan Lin 1
Unmesh Bordoloi 1
Marcelo Johann 1
Myungsun Kim 1
Hyojung Lee 1
Prasun Ghosal 1
Yuzhen Niu 1
Sandip Das 1
Ganesh Gopalakrishnan 1
LiehMing Wu 1
Hasan Arslan 1
Haibo Wang 1
Chuanjun Zhang 1
Farshad Firouzi 1
Tian Zhang 1
Fahimeh Jafari 1
Savithri Sundareswaran 1
Tomvander Aa 1
Mark Johnson 1
Stefan Pees 1
Heinrich Meyr 1
Alexios Birbas 1
Dmitri Maslov 1
Bita Gorjiara 1
Nader Bagherzadeh 1
Gang Chen 1
Bo Yao 1
Pingqiang Zhou 1
James Hoe 1
Tim Tuan 1
Olinto Furtado 1
Bradley Carlson 1
Yongsoo Joo 1
Donghwa Shin 1
Bren Mochocki 1
Weiyu Tang 1
Pejman Lotfi-Kamran 1
Mohammad Hosseinabady 1
Venkataramanan Balakrishnan 1
Carlos Fernández 1
Chris Bleakley 1
Shenghua Liu 1
Daniel Kroening 1
Jayanta Bhadra 1
John Pape 1
Xiaoke Qin 1
Prabhat Mishra 1
Eren Kursun 1
Hongting Lin 1
Siobhán Clarke 1
Padmaraj Singh 1
Michael Kishinevsky 1
Sarmishtha Ghoshal 1
Ankit More 1
Yan Jia 1
Chungwei Lin 1
Graeme Gange 1
Alan Hu 1
Xiaowei Li 1
Cristiana Bolchini 1
Su Gao 1
Feipei Lai 1
Doris Ching 1
Abusaleh Jabir 1
Andreas Raabe 1
Philipp Hartmann 1
George Viamontes 1
A Abbasian 1
David Bol 1
Paul Franzon 1
Chien Liu 1
Mango Chao 1
Nastaran Baradaran 1
Joachim Falk 1
Robert Johnson 1
Stefan Gheorghita 1
Andreas Hansson 1
Prasenjit Basu 1
Chiaheng Tu 1
Chengan Chien 1
Sounil Biswas 1
Gustavo Tellez 1
Seongseok Seo 1
Rafael Moreno 1
Mirko Loghi 1
Sri Parameswaran 1
Daler Rakhmatov 1
Younghwan Park 1
Vijay D'Silva 1
Kazuhisa Ishizaka 1
Xrysovalantis Kavousianos 1
Subhas Nandy 1
Joanna Ho 1
Richard Wong 1
Avi Ziv 1
Jos Hulzink 1
Arthur Yeh 1
Ruibing Lu 1
Sezer Gören 1
F Ferguson 1
Siddharth Jain 1
Jean Rolt 1
Scott Chilstedt 1
Rohit Ramanujam 1
Bill Lin 1
Jinho Lee 1
Bo Wang 1
Wonyong Sung 1
Mehrdad Majzoobi 1
Amit Agarwal 1
Chunan Chen 1
Duo Li 1
Michael Gester 1
Gary Tressler 1
Baoxian Zhao 1
Renyuan Zhang 1
Hamid Sarbazi-Azad 1
Steffen Peter 1
Changho Choi 1
Brentbyunghoon Kang 1
Hyungjun Kim 1
Arseniy Vitkovskiy 1
José Güntzel 1
Garng Huang 1
James Geraci 1
Saraju Mohanty 1
Priyank Gupta 1
Seetal Potluri 1
A Trinadh 1
Éric Rutten 1
Sebastien Guillet 1
Jean Diguet 1
Chunkai Wang 1
Chingyu Chin 1
Dejun Mu 1
Mohit Tiwari 1
Xueliang Li 1
Kiyin Chang 1
Ian Parberry 1
Yehia Massoud 1
Chichou Kao 1
Saurabh Adya 1
Qingfeng Zhuge 1
Sunil Chappidi 1
PoHsien Chang 1
WeiChung Chao 1
Song Liu 1
Ge Yu 1
John Emmert 1
Jinian Bian 1
Haikun Zhu 1
Werner Geurts 1
Johan Van Praet 1
Gang Chen 1
Hiroaki Suzuki 1
Tadao Yamanaka 1
Haruyuki Ohkuma 1
Eduardo Pacheco 1
Hamid Mahmoodi 1
Alex Kondratyev 1
Lihua Yue 1
Zhifang Li 1
Chengjuei Yu 1
YiHsin Wu 1
Niall O'Neill 1
Alessandro Bogliolo 1
Vincenza Carchiolo 1
Ted Szymanski 1
Udo Kebschull 1
Xiang Lu 1
Dana Price 1
Fernanda De Lima 1
Soumendu Bhattacharya 1
Min Xie 1
Krishna Palem 1
Eugenio Villar 1
Youngpyo Joo 1
SungKyu Lim 1
Wei Wu 1
Terrence Mak 1
Román Hermida 1
Nizar Dahir 1
Jianhua Li 1
Liang Shi 1
Mitchell Thornton 1
Alan Su 1
Mario Leung 1
Ryan Rakib 1
YuHsin Kuo 1
Muhammad Pasha 1
Amit Chowdhary 1
João Marques-Silva 1
Junxia Ma 1
John Lillis 1
Dian Zhou 1
Javier Resano 1
Daniel Mozos 1
KuangCyun Hsiao 1
Jingwei Lu 1
Chulhong Park 1
Qinke Wang 1
Sayantan Das 1
Michael Taylor 1
Yenchun Lin 1
Eddie Hung 1
SueHong Chow 1
Sudeep Pasricha 1
Karin Avnit 1
Yuru Hong 1
Philippe Grosse 1
Yves Durand 1
Owen Farell 1
Sanghyeon Baeg 1
Weitsun Sun 1
Sungkyu Lim 1
Kunhyuk Kang 1
Jason Cheatham 1
Mauricio Ayala-Rincón 1
Paul Pop 1
Traian Pop 1
Petru Eles 1
Hannahhonghua Yang 1
Qiang Zhou 1
Swanwa Liao 1
Gunar Schirner 1
Andreas Gerstlauer 1
Xue Liu 1
Somnath Paul 1
Heman Khanna 1
David Long 1
Mahesh Iyer 1
Fabrizio Lombardi 1
Yuan Cai 1
Xiaojian Yang 1
Stefan Obenaus 1
Naran Sirisantana 1
Kumar Parthasarathy 1
Hiren Patel 1
YoungMin Yi 1
Tathagato Dastidar 1
Lingling Jin 1
Pablo Del Valle 1
Giacomo Paci 1

Affiliation Paper Counts
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
New York University Abu Dhabi 1
Microsoft Research 1
University of Potsdam 1
New York University 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers University 1
Nortel Networks 1
Curtin University of Technology, Perth 1
Indian Institute of Technology Roorkee 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Gonzaga University 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Calgary 1
University of Texas at San Antonio 1
Universite de Bretagne-Sud 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
Hong Kong University of Science and Technology 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
University of Kaiserslautern 1
Nanjing University of Science and Technology 1
University of Kent 1
Auburn University 1
Oakland University 1
INRIA Rhone-Alpes 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Peking University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Washington State University Tri-Cities 1
National Taipei University 1
Michigan Technological University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Villanova University 2
University of Lisbon 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
Universitat Politecnica de Catalunya 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
University of Tubingen 2
Southern Methodist University 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
Hanyang University 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Swiss Federal Institute of Technology, Zurich 2
Alcatel-Lucent 2
Stony Brook University 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institut de Recherche en Informatique et Systemes Aleatoires 2
University of Pisa 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
Universite Grenoble Alpes 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Instituto Superior Tecnico 3
Korea University 3
University of Electronic Science and Technology of China 3
Bogazici University 3
Delft University of Technology 3
The University of Hong Kong 3
Chung Hua University 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
RWTH Aachen University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
Portland State University 3
University of Brasilia 3
University of Melbourne 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Milan 3
Universite de Rennes 1 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
Hunan University 3
University of Seville 3
University of Cyprus 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Zhejiang University 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
Louisiana State University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
Microsoft 4
IBM Austin Research Laboratory 4
Syracuse University 4
University of Dortmund 4
Ulsan National Institute of Science and Technology 4
Western Michigan University 5
Royal Institute of Technology 5
North Carolina State University 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
National University of Singapore 5
Fuzhou University 5
University of Bristol 5
University of North Texas 5
Agilent Technologies 5
Shanghai Jiaotong University 5
Swiss Federal Institute of Technology, Lausanne 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Indian Institute of Technology, Delhi 5
Nanjing University 5
Fujitsu America, Inc. 5
Karlsruhe Institute of Technology 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
University of Illinois 6
Nanyang Technological University 6
Fudan University 6
Brown University 6
Technical University of Lisbon 6
University of California, Davis 6
Holst Centre 6
University of Connecticut 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
Indian Institute of Technology, Madras 6
National Taiwan University of Science and Technology 6
University of Bologna 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
McGill University 7
University of Minnesota System 7
Linkoping University 7
HP Labs 7
University of Florida 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Technical University of Munich 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
University of California, Santa Cruz 7
State University of Campinas 7
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University of Wisconsin Madison 7
Iowa State University 8
Northwestern University 8
University of Waterloo 8
Federal University of Santa Catarina 8
University of Science and Technology of China 8
University of Notre Dame 8
University of Tehran 8
Indian Statistical Institute, Kolkata 8
University of Utah 8
Broadcom Corporation 8
Southern Illinois University at Carbondale 8
University of Michigan 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
Drexel University 9
Freescale Semiconductor 9
National Central University Taiwan 9
University of Freiburg 9
University of Illinois at Chicago 9
Princeton University 10
The University of British Columbia 10
Yuan Ze University 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
National University of Defense Technology China 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
Chung Yuan Christian University 10
NEC Corporation 10
Korea Advanced Institute of Science & Technology 10
University of Massachusetts Amherst 11
Imperial College London 11
University of Patras 11
Samsung Electronics 12
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
Academia Sinica Taiwan 12
University of Texas at Dallas 13
Catholic University of Leuven 13
University of Southern California 13
University of South Florida Tampa 14
National Chung Cheng University 14
Chinese Academy of Sciences 14
Complutense University of Madrid 14
University of California, Berkeley 15
University of Erlangen-Nuremberg 16
University of Arizona 17
Pennsylvania State University 18
Arizona State University 18
IBM 18
Tsinghua University 18
Virginia Tech 18
Cadence Design Systems 18
Ghent University 18
Chinese University of Hong Kong 19
University of California, Santa Barbara 19
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
National Cheng Kung University 23
University of Maryland 26
Eindhoven University of Technology 26
Duke University 28
Synopsys Incorporated 28
University of Texas at Austin 30
Intel Corporation 30
Purdue University 31
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
Carnegie Mellon University 35
University of Pittsburgh 36
University of California, Riverside 39
National Taiwan University 40
National Chiao Tung University Taiwan 42
Texas A and M University 42
University of California, San Diego 43
Indian Institute of Technology, Kharagpur 45
Seoul National University 60
University of California, Irvine 63
National Tsing Hua University 63
University of California, Los Angeles 65

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Volume 21 Issue 2, January 2016

Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Volume 20 Issue 3, June 2015
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Volume 20 Issue 1, November 2014
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Volume 19 Issue 1, December 2013
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Volume 18 Issue 3, July 2013
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Volume 17 Issue 4, October 2012
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Volume 16 Issue 4, October 2011
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Volume 16 Issue 1, November 2010
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Volume 15 Issue 1, December 2009
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Volume 3 Issue 4, Oct. 1998
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Volume 2 Issue 4, Oct. 1997
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Volume 1 Issue 4, Oct. 1996
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