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Eh?Placer

The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent ACM/IEEE International Symposium on Physical Design (ISPD) contests. In this article, the framework of... (more)

Clock-Tree-Aware Incremental Timing-Driven Placement

The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step toward timing closure.... (more)

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective... (more)

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address... (more)

Analytical Clustering Score with Application to Postplacement Register Clustering

Circuit clustering is usually done through discrete optimizations to enable circuit size reduction or design-specific cluster formation. In this... (more)

PARR

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, for example, in 14nm and below, for which double-patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches, such as M2 and M3. Self-aligned double patterning (SADP) provides better control on line... (more)

EBL Overlapping Aware Stencil Planning for MCC System

Electron beam lithography (EBL) is a promising, maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation,... (more)

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been... (more)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout

In the MOS analog layout, variability suppression is becoming a major issue, as is layout efficiency. Introducing a transistor array (TA) style to... (more)

NEWS

Best Paper Award: Congratulations to Chung-Wei Lin, Bowen Zheng, Qi Zhu, and Alberto Sangiovanni-Vincentelli on receiving the 2016 ACM TODAES Best Paper Award for their article titled Security-Aware Design Methodology and Optimization for Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1, Article 18, November 2015.

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

Forthcoming Articles
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), the on-chip networks are facing serious challenges in providing fast communication for various tasks and cores. One promising on-chip network design shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behav-iors, both of which have not been fully exploited in existing mapping algorithms. In this paper, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened but-terfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

On the Restore Time Variations of Future DRAM Memory

As the de facto main memory standard, DRAM has achieved dramatic density improvement in the past four decades, along with the advancements in process technology. Recent studies reveal that one of the major challenges in scaling DRAM into deep sub-micron regime is its significant variations on cell restore time, which affect timing constraints such as write recovery time tWR. Adopting traditional approaches results in either low yield rate or large performance degradation. In this paper, we propose schemes to expose the variations to the architectural level. By constructing memory chunks with different access speeds and, in particular, exploiting the performance benefits of fast chunks, a variation-aware memory controller can effectively mitigate the performance loss due to relaxed timing constraints. We then proposed restore time aware rank construction and page allocation schemes to make better use of fast chunks. Our experimental results show that, comparing to traditional designs such as row sparing and ECC, the proposed schemes help to improve system performance by about 16% and 20%, respectively, for 20nm and 14nm technology nodes on a four-core multiprocessor system.

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

Hierarchical Statistical Leakage Analysis and Its Application

In this paper, we investigate a hierarchical statistical leakage analysis design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power analysis. To solve the challenges of incorporating spatial correlations between IP modules at system level, we first propose a method to extract correlation-inclusive leakage models. Then a method to handle the spatial correlations at system level is also proposed. Using this method the runtime of system statistical leakage analysis can be significantly improved without disclosing the netlists of the IP modules. Experimental results demonstrate that the proposed hierarchical statistical leakage analysis method is about 100 times faster than the gate-level full-chip statistical leakage analysis methods while the accuracy of statistical leakage analysis is still well maintained. In addition, we also investigate one application of this hierarchical statistical leakage analysis method, a leakage-yield-driven floorplanning framework, to demonstrate the benefits of such hierarchical statistical leakage analysis method in practice. At the same time, we also propose an optimized hierarchical leakage analysis method dedicated for the floorplanning framework. The effectiveness of the floorplanning framework and the optimized method is also confirmed by the experimental results.

Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow

The Scenario-Aware Dataflow (SADF) model is based on concurrent actors that interact via channels. It combines streaming data and control to capture scenarios while incorporating hard and soft real-time aspects. To model data-flow computations that are subject to uncertainty, SADF models are equipped with random primitives. We propose to use probabilistic model checking to analyse uncertain SADF models. We show how measures such as expected time, long-run objectives like throughput, as well as timed reachability can a given system configuration be reached within a deadline with high probability?can be automatically determined. The crux of our method is a compositional semantics of SADF with exponential agent execution times combined with automated abstraction techniques akin to partial-order reduction. We present the semantics in detail, and show how it accommodates the incorporation of execution platforms enabling the analysis of energy consumption. The feasibility of our approach is illustrated by analysing several quantitative measures of an MPEG-4 decoder and an industrial face recognition application.

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems

During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of non-volatile flash in the systems memory hierarchy. The increasing capacity of NAND flash memory introduces large RAMfootprint to store the logical to physical address mapping. The demand-based approach can effectively reduce and well control the RAM footprint. However, extra address translation overhead is also introduced which may degrade the system performance. In this paper, we present CDFTL, an adaptive Caching mechanism for Demand-based Flash Translation Layer, for NAND flash memory storage systems. CDFTL adopts both the fine-grained entry-based caching mechanismto exploit temporal locality and the coarse-grained translation-page-based cachingmechanism to exploit spatial locality of workloads. By selectively caching the on-demand address mappings and adaptively changing the space configurations of two granularities, CDFTL can effectively utilize the RAM space and improve the cache hit ratio. We evaluate CDFTL under a real hardware embedded platform using a variety of I/O traces. Experimental results show that our technique can achieve a 11.13% reduction in average system response time and a 35.21% reduction in translation block erase counts compared with the previous work.

Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors

It is challenging to manage the thermal behavior of many-core microprocessors while still keep it running at high-performance since control complexity increases as core number increases. In this paper, a novel hierarchical dynamic thermal management method is proposed to overcome this challenge. The new method employs model predictive control (MPC) with task migration and DVFS scheme to ensure smooth control behavior and negligible computing performance sacrifice. In order to be scalable to many-core system, the hierarchical control scheme is designed with two levels. At the lower level, the cores are spatially clustered into blocks, and local task migration is used to match current power distribution with the optimal distribution calculated by MPC. At the upper level, global task migration is used with the unmatched powers from the lower level. A modified iterative minimum cut algorithm is used to assist the task migration decision making if the power number is large at the upper level. Finally, DVFS is applied to regulate the remaining unmatched powers. Experiments show that the new method is highly scalable to many-core microprocessors with little computing performance compromises and outperforms existing methods.

A Fast and Scalable Multi-dimensional Multiple-choice Knapsack Heuristic

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredicatability is an important security feature of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In existing literature on PUFs, Hamming Distance test, denoted by HDT(t), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC(t). The objective of these test schemes is to estimate the output transition probability when there are t or less than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test which is denoted as HDT(e,t). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t. As a contribution, we provide a comprehensive discussion and analytic interpretation of the HDT(t), PC(t) and HDT(e,t) test schemes for Arbiter PUF (APUF), XOR PUF and Lightweight Secure PUF (LSPUF). Our analysis establishes that the HDT(e,t) test is more general in comparison with HDT(t) and PC(t) tests. In addition, we demonstrate scenarios where the adversary can exploit the information obtained from the analysis of HDT(e,t) properties of APUF, XOR PUF and LSPUF to develop statistical attacks on them, if the ideal value of HDT(e,t)=0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and FPGA implemented APUF, XOR PUF and LSPUF designs.

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip

Digital (droplet-based) microfluidic technology offers an attractive platform for implementing a wide variety of biochemical laboratory protocols, such as point-of-care diagnosis, DNA analysis, target detection, and drug discovery. However, because of the inherent uncertainty of fluidic operations, the outcome of biochemical experiments performed on-chip can be erroneous even if the chip is tested a priori and deemed to be defect-free. In this paper, we address an important error-recoverability problem in the context of sample preparation. We assume a cyberphysical environment, in which the physical errors, when detected online at selected checkpoints with integrated sensors, can be corrected through recovery techniques. However, almost all prior work on error recoverability used a checkpointing-based rollback approach, i.e., re-execution of certain portion of the protocol starting from the previous checkpoint. Unfortunately, such techniques are expensive both in terms of assay-completion time and reagent cost, and can never ensure full error-recovery in a deterministic sense. We consider imprecise droplet mix-split operations and present a novel roll-forward approach where the erroneous droplets, thus produced, are used in the error-recovery process, instead of being discarded or re-mixed. All erroneous droplets participate in the dilution process and they mutually cancel or reduce the concentration error when the target droplet is reached.We also present a rigorous analysis that discovers the role of volumetric error on the concentration of a sample to be prepared, and we describe the layout of a lab-on-chip that can execute the proposed cyberphysical dilution algorithm. Our analysis reveals that fluidic errors caused by unbalanced droplet splitting can be classified as being either critical or non-critical, and only those of the former type require correction to achieve error-free sample dilution. Simulation experiments on various sample preparation test cases demonstrate the effectiveness of the proposed method.

ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems

Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and QoS guarantees on multiprocessors, form an attractive alternative in real-time embedded systems that concurrently run a mix of independent applications with varying timeliness constraints. This paper presents "ERfair Scheduler with Suspension on Multiprocessors" (ESSM), an efficient, optimal proportional fair scheduler that attempts to reduce system wide energy consumption by locally maximizing the processor suspension intervals while not sacrificing the ERfairness timing constraints of the system. The proposed technique takes advantage of higher execution rates of tasks in underloaded ERfair systems and uses a procrastination scheme to search for time points within the schedule where suspension intervals are locally maximal. Evaluation results reveal that ESSM achieves good sleep efficiency and provides upto 50% higher effective total sleep durations as compared to the Basic-ERfair scheduler on systems consisting of 2 to 20 processors.

Non-enumerative Generation of Path Delay Distributions and its Application to Critical Path Selection

A Monte Carlo based approach is proposed capable of identifying in a path-implicit and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

System Level Design Approaches to Security in Automotive Networks

With the increasing amount of interconnections between vehicles, the attack surface of internal vehicle networks is rising steeply. Although these networks are shielded against external attacks, they often do not have any internal security to protect against malicious components or adversaries who can breach the network perimeter. To secure the in-vehicle network, all communicating components must be authenticated, and only authorized components should be allowed to send and receive messages. This is achieved through an authentication framework. Cryptography is widely used to authenticate communicating parties and provide secure communication channels (e.g. Internet communication). However, real-time performance requirements of in-vehicle networks restrict the types of cryptographic algorithms and protocols that may be used. In particular, asymmetric cryptography is computationally infeasible during vehicle operation. In this work, we address the challenges of designing authentication protocols for automotive systems. We present Lightweight Authentication for Secure Automotive Networks (LASAN), a full life-cycle authentication approach. We describe the LASAN protocols and show how they protect the internal vehicle network while complying with the real-time constraints and low computational resources of this domain. Unlike previous work, we also explain how LASAN can be integrated into all aspects of the automotive product life cycle, including manufacturing and maintenance. We evaluate LASAN in two ways: Firstly, we analyze the security of the protocols using established protocol verication based on formal methods. Secondly, we evaluate the timing requirements of LASAN and compare these to other frameworks using a new discrete event simulator for in-vehicle networks.

A Compact Implementation of Salsa20 and its Power Analysis Vulnerabilities

In this paper, we present a compact implementation of Salsa20 stream cipher that is targeted towards lightweight cryptographic devices such as RFID tags. The Salsa20 stream cipher, an ARX cipher, is used in high security cryptography in NEON instruction set embedded in ARM-based tablets and smartphones. The existing literature shows that though classical cryptanalysis has been effective on reduced rounds of Salsa20, the stream cipher is immune to software side-channel attacks such as branch timing and cache timing attacks. To the best of our knowledge, this work is the first to perform hardware power analysis attacks, where we evaluate the resistance of all the eight keywords in the proposed compact implementation of Salsa20. Our technique targets the three subrounds of the first round of the implemented Salsa20. The CPA attack has an attack complexity of $2^{19}$. Based on extensive experiments on a compact implementation of Salsa20, we demonstrate that all these keywords can be recovered within $20000$ queries on Salsa20. The attacks show a varying resilience of the key words against correlation power analysis (CPA) that has not yet been observed in any stream or block cipher in present literature. This makes the architecture of this stream cipher interesting from the side-channel analysis perspective. Also, we propose a light-weight countermeasure which mitigates the leakage in the power traces as shown in the results of Welch's $t$-test statistics. The hardware area overhead of the proposed countermeasure is only $14\%$ and is designed with compact implementation in mind.

DReAM: an Approach to Estimate Per-Task DRAM Energy in Multicore Systems

Per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction between tasks in shared resources, which impacts tasks' energy consumption in uncontrolled ways. Some accurate mechanisms have been devised recently to estimate per-task energy consumed on-chip in multicores, but there is a lack of such mechanisms for DRAM memories. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations. In particular, the contributions of this paper are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate, yet low cost, implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is more accurate than these other methods

Area-aware Decomposition for Single-Electron Transistor Arrays

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moores law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large reconfigurable SET array where the height of SET array equals the number of primary inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say 10, rather than arbitrary value due to the ultra-low driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large SET array into a set of small SET arrays where each of them realizes a subfunction of the original circuit with no more than 10 inputs. Thus, this paper presents two techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced. The width minimization algorithm leads to a 25%~41% improvement compared to the state-of-the-art, and the mapping algorithm achieves a 60% reduction in total area compared to a nai1ve approach.

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement

Routability is one of the most important problems in high performance circuit designs. From the viewpoint of placement design, two major factors cause routing congestion: 1) interconnections between cells, and 2) connections on macro blockages. In this paper, we present a routability-driven placer Ripple 2.0 which emphasizes both kinds of routing congestion. Several techniques will be presented, including 1) cell inflation with routing path consideration, 2) congested cluster optimization, 3) routability-driven cell spreading, and 4) simultaneous routing and placement for routability refinement. With the official evaluation protocol, Ripple 2.0 outperforms other published academic routability-driven placers. Compared with top results in ICCAD 2012 contest, Ripple 2.0 achieves better detailed routing solution obtained by a commercial router.

Optimized Implementation of Multi-Rate Mixed-Criticality Synchronous Reactive Models

Model-based design using Synchronous Reactive (SR) models enables early verification of functionality, and helps to cope with the increasing complexity of modern embedded systems. Mixed-Criticality Scheduling (MCS) is an effective approach to addressing diverse certification requirements of safety-critical systems that integrate multiple subsystems with different levels of criticality. This paper considers fixed-priority scheduling of mixed-criticality SR models, and explores two scheduling techniques: one is based on Adaptive Mixed-Criticality scheduling, the other based on Elastic Mixed-Criticality Scheduling. We present a branchand- bound procedure and a heuristic algorithm to minimize the total system cost of functional delays in the implementation.

Hybrid Power Management for Office Equipment

Office machines (such as printers, scanners, fax, and copiers) can consume significant amounts of power. Most office machines have sleep modes to save power. Power management of these machines are usually timeout-based: a machine sleeps after being idle long enough. Setting the timeout duration can be difficult: if it is too long, the machine wastes power during idleness. If it is too short, the machine sleeps too soon and too often the wakeup delay can significantly degrade productivity. Thus, power management is a tradeoff between saving energy and keeping response time short. Many power management policies have been published and one policy may outperform another in some scenarios. There is no definite conclusion which policy is always better. This paper describes two methods for office equipment power management. The first method adaptively reduces power based on a constraint of the wakeup delay. The second method is a hybrid method with multiple candidate policies and it selects the most appropriate power management policy. Using six months of request traces from 18 different printers, we demonstrate that the hybrid policy outperforms individual policies. We also discover that power management based on business hours does not produce consistent energy savings.

Critical-Path-Aware High-Level Synthesis with Distributed Controller for Fast Timing Closure

Partitioning and Data Mapping in Reconfigurable Cache and ScratchPad Memory based Architectures

Scratch Pad memory (SPM) is considered a useful component in the memory hierarchy, solely or along with caches, to meet the power and energy constraints as performance ceases to be the sole criteria for processor design. Although the efficiency of SPM is well known, its usage has been restricted owing to difficulties in programmability. Real applications usually have regions that are amenable to exploitation by either SPM or cache, and hence can benefit if the two are used in conjunction. Dynamically adjusting the local memory resources to suit application demand, can significantly improve the efficiency of the overall system. In this paper, we propose a compiler technique to map application data objects to SPM/cache and also partition the local memory between SPM and cache depending on the dynamic requirement of the application. First, we introduce a novel graph based structure to tackle data allocation in an application. Second, we use this to present a data allocation heuristic to map program objects for a fixed sized SPM-cache hybrid system that targets whole program optimization. We finally extend this formulation to adapt the SPM and cache sizes, as well as the data allocation as per the requirement of different application regions. We study the applicability of the technique on various workloads targeted at both SPM-Only and hardware reconfigurable memory system, and observe an average of 18% energy-delay improvement over state-of-the-art techniques.

Scalable SMT-based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis

In this paper, we present a novel methodology based on SMT-solvers to verify equality of a high level described specification and a pipelined RTL implementation produced by a high level synthesis tool. The complex transformations existing in the high level synthesis process, such as nested loop pipelining, cause the conventional methods of equivalence checking to be inefficient. The proposed equivalence checking method attacks simultaneously to the two problems in this context: 1) state space explosion and 2) complex high level synthesis transformations. To show the scalability and efficiency of the proposed method, the verification results of large industrial designs are compared with those of the SAT-based method, including three different state-of-the-art SAT-solvers, the SMT-based procedure, the modular Horner expansion diagram (M-HED) based method, and the M-HED partitioning approach. The results show interesting improvements in terms of time and memory usage in comparison with other methods. Furthermore, using the proposed equivalence checking approach, fault tolerance issues can be formally analyzed in the presence of some faults in the designs.

Genetic Algorithm Based FPGA Architectural Exploration using Analytical Models

FPGA architectural optimization has emerged as one of the most important digital design challenges. Recent years, experimental methods have been replaced by analytical ones to find the optimized architecture. Time is the main reason for this replacement. Conventional Geometric Programming (GP) is a routine framework to solve analytical models; including area, delay and power models. In this paper, we discuss the application of Genetic Algorithm (GA) to the design of FPGA architectures. The performance model has been integrated into the Genetic Algorithm framework in order to investigate the impact of various architectural parameters on the performance-efficiency of FPGAs. This way, we are able to rapidly analyze FPGA architectures and select the best one. The main advantages of using GA versus GP are concurrency and speed. The results show that concurrent optimization of high-level architecture parameters including Look-up Table size (K) and Cluster size (N) and low-level parameters like scaling of transistors is possible for GA, whereas GP does not capture K and N under its concurrency and it needs to exhaustively search all possible combinations of K and N. The results also show that up to 104´ run time improvement in comparison with GP based analysis is achieved.

Reducing the Complexity of Dataflow Graphs using Slack-based Merging

There exist many dataflow applications with timing constraints that require real-time guarantees on safe execution without violating their deadlines. Extraction of timing parameters (offsets, deadlines, periods) from these applications enables the use of real-time scheduling and analysis techniques, and provides guarantees on satisfying timing constraints. However, existing extraction techniques require the transformation of the dataflow application from highly expressive dataflow computational models, e.g., Synchronous Dataflow (SDF) and Cyclo-Static Dataflow (CSDF) to Homogeneous Synchronous Dataflow (HSDF). This transformation can lead to an exponential increase in the size of the application graph that significantly increases the run-time of the analysis. In this article, we address this problem by proposing an algorithm called slack-based merging that generates a reduced-size HSDF graph from a given SDF graph with timing constraints. This algorithm is based on a novel concept of merging called safe merge, which is a merge operation that we formally prove that it cannot cause a live HSDF graph to deadlock. The results show that the reduced graph: 1) respects the throughput and latency constraints of the original application graph and 2) typically speeds up the process of extracting timing parameters and finding a feasible real-time schedule for real-time dataflow applications. They also show that when the throughput constraint is relaxed with respect to the maximal throughput of the graph, the merging algorithm is able to achieve a larger reduction in graph size, which in turn results in a larger speed-up of the real-time scheduling algorithms.

Bibliometrics

Publication Years 1996-2016
Publication Count 866
Citation Count 4057
Available for Download 866
Downloads (6 weeks) 2155
Downloads (12 Months) 22630
Downloads (cumulative) 350935
Average downloads per article 405
Average citations per article 5
First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Distinguished Member (2008)
ACM Senior Member (2006)
Nikil D. Dutt ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
Soheil Ghiasi ACM Senior Member (2015)
Matthew Guthaus ACM Senior Member (2013)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
John Lee ACM Senior Member (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Ian Parberry ACM Distinguished Member (2015)
Massoud Pedram ACM Distinguished Member (2008)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
Robert Schreiber ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 17
Nikil Dutt 15
Irith Pomeranz 14
Krishnendu Chakrabarty 12
Jason Cong 12
Tingting Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
Sheldon Tan 9
Lei He 8
Yaowen Chang 8
Yunheung Paek 7
Frank Vahid 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Spyros Tragoudas 6
Taewhan Kim 6
Martin Wong 6
Alexandru Nicolau 6
John Hayes 6
Ryan Kastner 6
Chengkok Koh 6
Massoud Pedram 6
Radu Marculescu 6
Sudhakar Reddy 6
Igor Markov 6
Evangeline Young 5
Ali Dasdan 5
Sule Ozev 5
Sharad Malik 5
David Pan 5
Kiyoung Choi 5
Bhargab Bhattacharya 5
Kaushik Roy 5
Mahmut Kandemir 5
Umit Ogras 5
Jenqkuen Lee 5
Rajeev Kumar 5
Aviral Shrivastava 5
Giovanni De Micheli 5
Andrew Kahng 5
Tony Givargis 5
Roman Lysecky 5
Nagarajan Ranganathan 5
Chungkuan Cheng 5
Kwangting Cheng 4
Rajesh Gupta 4
Zijiang Yang 4
Sunil Khatri 4
El Aboulhamid 4
Jingyang Jou 4
Aarti Gupta 4
Xiaobosharon Hu 4
Pinghung Yuh 4
Shihhsu Huang 4
Peng Li 4
Peter Petrov 4
Iris Jiang 4
Alex Jones 4
Ramesh Karri 4
Hungming Chen 4
Sunyuan Hsieh 4
Yuanhao Chang 4
Hans Wunderlich 4
Chang Liu 4
Jintai Yan 4
Allen Wu 4
Naehyuck Chang 4
Preeti Panda 4
Miodrag Potkonjak 4
Jongeun Lee 4
Dinesh Mehta 4
Paul Gratz 4
Franco Fummi 4
Paulo Flores 4
Hai Zhou 4
Dirk Stroobandt 4
Chakkuen Wong 3
Waikei Mak 3
Krishnendu Chakrabarty 3
Teiwei Kuo 3
Seda Memik 3
Henk Corporaal 3
Dimitrios Kagaris 3
Martin Lukasiewycz 3
Praveen Raghavan 3
Karel Bruneel 3
Soonhoi Ha 3
Valeria Bertacco 3
Viktor Prasanna 3
Yuan Xie 3
Diana Marculescu 3
Ronald Blanton 3
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Bill Lin 1
Manoj Sachdev 1
Adit Singh 1
Turker Kuyel 1
Gustavo Neuberger 1
Lakshmi Chakrapani 1
Chiennan Liu 1
Chiachun Tsai 1
Gustavo Tellez 1
Seongseok Seo 1
Rafael Moreno 1
Arne Meeuw 1
Taeyoung Kim 1
Hai Wang 1
Vikas Vij 1
Jiang Hu 1
Philipp Mundhenk 1
Jingweijia Tan 1
Daler Rakhmatov 1
Mirko Loghi 1
Vijay D'Silva 1
Sri Parameswaran 1
Younghwan Park 1
Kazuhisa Ishizaka 1
Xrysovalantis Kavousianos 1
Subhas Nandy 1
Joanna Ho 1
Richard Wong 1
Avi Ziv 1
Jos Hulzink 1
Sezer Gören 1
F Ferguson 1
Dian Zhou 1
John Emmert 1
Arthur Yeh 1
Ruibing Lu 1
Jinian Bian 1
Haikun Zhu 1
Gang Chen 1
Werner Geurts 1
Johan Van Praet 1
Eduardo Pacheco 1
Hiroaki Suzuki 1
Tadao Yamanaka 1
Haruyuki Ohkuma 1
Hamid Mahmoodi 1
Alex Kondratyev 1
Zhifang Li 1
Lihua Yue 1
Chengjuei Yu 1
YiHsin Wu 1
Kazutoshi Wakabayashi 1
Etem Deniz 1
Xuchu Hu 1
Angchih Hsieh 1
Olinto Furtado 1
Tim Tuan 1
Yongsoo Joo 1
Donghwa Shin 1
Moritz Schmid 1
Sandip Kundu 1
Ryan Cochran 1
Atsuto Hanami 1
Juyueh Lee 1
Weifeng He 1
Juan Clemente 1
Kuolin Peng 1
Denis Flandre 1
Steven Nowick 1
Renyuan Zhang 1
Gary Tressler 1
Hyungjun Kim 1
Arseniy Vitkovskiy 1
Hamid Sarbazi-Azad 1
Steffen Peter 1
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Zainalabedin Navabi 1
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Calin Ciordas 1
Stefan Pees 1
Heinrich Meyr 1
Hui Huang 1
Luc Bianco 1
Giuseppe Mangioni 1
Pradip Jha 1
Miron Abramovici 1
Ingrid Verbauwhede 1
Robert Rinker 1
Ugur Sezer 1
Chunkai Wang 1
Chingyu Chin 1
Dejun Mu 1
Mohit Tiwari 1
Xueliang Li 1
Bren Mochocki 1
Weiyu Tang 1
Pejman Lotfi-Kamran 1
Mohammad Hosseinabady 1
Robert Schreiber 1
Meenakshi Kaul 1
J Ramanujam 1
Dipankar Sarkar 1
Ted Szymanski 1
Udo Kebschull 1
Soumendu Bhattacharya 1
Min Xie 1
Nizar Dahir 1
Terrence Mak 1
Jianhua Li 1
Liang Shi 1
Mitchell Thornton 1
Alan Su 1
Mario Leung 1
Muhammad Pasha 1
Ryan Rakib 1
YuHsin Kuo 1
Junxia Ma 1
Gianpiero Cabodi 1
Debapriya Chatterjee 1
Yiding Han 1
Antonio Pérez 1
Jay Brockman 1
Praveen Murthy 1
Jiunlang Huang 1
Bijan Alizadeh 1
AnPing Wang 1
Pai Chou 1
Tiansi Hu 1
Robert Dick 1
YongHwan Kim 1
Mohammed Khatib 1
ChoonYik Tang 1
Waichung Tang 1
Jinjun Xiong 1
David Blaauw 1
ChunDa Du 1
Chunghsiang Lin 1
Miad Faezipour 1
Byunghyun Lee 1
Ken Kennedy 1
Yuzheng Ding 1
David Whalley 1
Ingjer Huang 1
Sharat Prasad 1
ChuangYi Chiu 1
Bruno Lavigueur 1
D Van Campenhout 1
Trevor Mudge 1
Alex OrailoĞLu 1
Saraju Mohanty 1
James Geraci 1
Priyank Gupta 1
Seetal Potluri 1
A Trinadh 1
Sebastien Guillet 1
Éric Rutten 1
Jean Diguet 1
Chulhong Park 1
Qinke Wang 1
Jingwei Lu 1
Sayantan Das 1
Michael Taylor 1
Yenchun Lin 1
SueHong Chow 1
Eddie Hung 1
Ujjwal Guin 1
Guoqing Chen 1
David Hély 1
Liang Chen 1
Yongpan Liu 1
Song Jin 1
Huawei Li 1
Karin Avnit 1
Sudeep Pasricha 1
Yuru Hong 1
Philippe Grosse 1
Yves Durand 1
Owen Farell 1
Sanghyeon Baeg 1
Weitsun Sun 1
Sungkyu Lim 1
Kunhyuk Kang 1
Jason Cheatham 1
Mauricio Ayala-Rincón 1
Hannahhonghua Yang 1
Qiang Zhou 1
Paul Pop 1
Traian Pop 1
Petru Eles 1
Swanwa Liao 1
Somnath Paul 1
Gunar Schirner 1
Andreas Gerstlauer 1
Xue Liu 1
Yuan Cai 1
Ricardo Reis 1
Rick McGeer 1
Ilia Polian 1
Zhihua Zhou 1
Dennis Huang 1
Chungkuan Cheng 1
Dong Lee 1
Hsueh Lu 1
Arijit Ghosh 1
C Krishna 1
Geert Deconinck 1
Nobuhiro Tsuda 1
Donatella Sciuto 1
Kaijie Wu 1
Wennai Cheng 1
Guoqiang Chen 1
Waseem Ahmed 1
Michael Glaß 1
Zhiying Wang 1
Jieun Lim 1
Nagesh Lakshminarayana 1
Bernd Becker 1
Kamyiu Lam 1
Chiawei Lee 1
Xuan Guan 1
Yunchih Chang 1
Bailey Miller 1
Brian Tagiku 1
Ashish Gupta 1
Hungming Chen 1
Christian Schulte 1
Jun Lu 1
Songbin Pan 1
Gungyu Pan 1
Kunlin Tsai 1
Kijin Han 1
Youngmin Kim 1
Mark Lin 1
Toru Fujimura 1
Sangmin Kim 1
Chiying Tsui 1
Peishan Tu 1
Chen Zhao 1
Tong Xu 1
Navin Vemuri 1
Chao Wang 1
Stefan Holst 1
Yi Zou 1
Michael Imhof 1
Rajeev Jayaraman 1
Chincheng Kuo 1
Éamonn Linehan 1
Chandan Karfa 1
Stefan Obenaus 1
Xiaojian Yang 1
Fabrizio Lombardi 1
Naran Sirisantana 1
Alex Yakovlev 1
Yinlong Xu 1
Christoph Kern 1
Zhaoliang Pan 1
Wei Zhao 1
Sreejit Chakravarty 1
Hungyi Li 1
Vladimir Zolotov 1
Stefano Quer 1
Henrik Esbensen 1
Li Shang 1
Zhuo Feng 1
Maria García 1
Santiago Rodríguez 1
Marc Heijligers 1
Weitong Chuang 1
Einar Aas 1
Sagar Sabade 1
Xiaoping Tang 1
Jaehwanjohn Lee 1
Subhankar Mukherjee 1
Ruijing Shen 1
Diederik Verkest 1
Pallab Dasgupta 1
David Kolson 1
Jun Chen 1
Bruno Girodias 1
Kuochen Wang 1
Youcef Bouchebaba 1
Gabriela Nicolescu 1
Hakan Yalcin 1
Swaroop Ghosh 1
QingPing Tan 1
Maurice Bruynooghe 1
Jinfeng Liu 1
Karam Chatha 1
Franck Yonga 1
Ling Li 1
Yunji Chen 1
Chinchi Teng 1
Hongfei Wang 1
Jiunin Guo 1
Zhuo Li 1
Sandip Kundu 1
Davide Rossi 1
Luca Benini 1
Roozbeh Jafari 1
Milagros Férnandez 1
Vinita Vasudevan 1
Jaeyeon Won 1
Jun Ma 1
Yu Hu 1
Mojtaba Ebrahimi 1
Mingsong Chen 1
Laurence Pierre 1
Youngsik Kim 1
Prosenjit Gupta 1
Srinivas Patil 1
Apostolos Kountouris 1
Elisenda Roca 1
Pallav Gupta 1
Takyung Kim 1
Harmke De Groot 1
Arpit Joshi 1
Wei Dong 1
Wei Li 1
Jan Stuijt 1
Fayez Mohamood 1
Carlos Llanos 1
Sanjukta Bhanja 1
Ishwar Parulkar 1
Abusaleh Jabir 1
Andreas Raabe 1
Philipp Hartmann 1
George Viamontes 1
Ningde Xie 1
Tong Zhang 1
Hyungjun Kim 1
Tan Yan 1
Si Li 1
Dana Price 1
Xiang Lu 1
Fernanda De Lima 1
Reiley Jeyapaul 1
Sungkyu Lim 1
Wei Wu 1
Krishna Palem 1
Román Hermida 1
Eugenio Villar 1
Youngpyo Joo 1
Davide Bertozzi 1
Kishore Muchherla 1
Luiz Santos 1
Brett Brotherton 1
Panagiotis Manolios 1
Christopher Batten 1
Wilsin Gosti 1
Manuel Prieto 1
Yiwen Shi 1
Srinivas Boppu 1
R Iris Bahar 1
Shravan Muddasani 1
John Lee 1
Luca Benini 1
Zhe Feng 1
Zhigang Mao 1
Chien Liu 1
Hiroyuki Kondo 1
Nastaran Baradaran 1
David Bol 1
Paul Franzon 1
Mango Chao 1
Cong Xu 1
Shimeng Yu 1
Stavros Hadjitheophanous 1
Yingchi Li 1
Mohammad Samavatian 1
Anand Raghunathan 1
Chibang Kuan 1
Phillip Jones 1
Ahcène Bounceur 1
Jinnshyan Wang 1
ChengTsung Hwang 1
Chengyang Fu 1
Sudhakar Muddu 1
Xiaoyao Liang 1
Alan Mishchenko 1
Shichun Tsai 1
Qiang Dou 1
Luis Bathen 1
Chienchin Huang 1
Suming Lai 1
Dionisios Pnevmatikatos 1
Dirk Muller 1
Hao Shen 1
Selvaraj Ravi 1
Nadereh Hatami 1
Reinhard Schneider 1
Peng Li 1
Chang Xu 1
Peixin Li 1
Xiaoqing Xu 1
Reeshav Kumar 1
Pangbo Wu 1
Andrew Kennings 1
Ramachandran Venkatasubramanian 1
Jian Liu 1
Qi Zhang 1
Heejong Park 1
Mohammed Ehteshamuddin 1
Vinay Verma 1
Sara Vinco 1
PoHsien Chang 1
WeiChung Chao 1
Mahir Turkcan 1
Deming Chen 1
Jaekyu Lee 1
Kumar Parthasarathy 1
Lingling Jin 1
Pablo Del Valle 1
Giacomo Paci 1
Hiren Patel 1
YoungMin Yi 1
Tathagato Dastidar 1
Nikhil Saluja 1
Mohamed Bechara 1
Murli Tirumala 1
Mingxuan Yuan 1
Rei Akiyama 1
Xiuqiang He 1
Wenjian Luo 1
Talal Bonny 1
Shengde Wang 1
Kyoungwoo Lee 1
Michel Israel 1
Norbert Wehn 1
Anup Gangwar 1
Hiroyuki Tomiyama 1
Benjamin Schafer 1
Wooyoung Jang 1
Matin Hashemi 1
Haifeng Qian 1
Guilherme Flach 1
Yenlung Chen 1
Eamonn O'Toole 1
Marisa López-Vallejo 1
Subhrajit Bhattacharya 1
M Narasimhan 1
Fred Meyer 1
Gary Yeap 1
Qi Wang 1
Balakrishnan Iyer 1
Zhong Wang 1
Gokul Kandiraju 1
Xiao Liu 1
Shyhjye Jou 1
Guoyong Shi 1
Ulf Schlichtmann 1
Eduardo Costa 1
Tayung Liu 1
Kerstin Eder 1
Sean Liu 1
Fatma Abouelella 1
Tom Davidson 1
Yumin Lee 1
Yifang Liu 1
Sylvain Clerc 1
Fabian Firmin 1
Xiongfei Liao 1
Antonio Garcia-Dopico 1
Adrian Nunez-Aldana 1
Yici Cai 1
Chris Chu 1
Fangfang Li 1
Ran Wang 1
Scott Mahlke 1
Andreas Hoffmann 1
Feipei Lai 1
Su Gao 1
Vincenza Carchiolo 1
Niall O'Neill 1
Alessandro Bogliolo 1
Doris Ching 1
Roopak Sinha 1
Mohamed Basiri M 1
Noor Sk 1
Shobha Vasudevan 1
Mateo Valero 1
Hsienkai Kuo 1
Zainalabedin Navabi 1
Amit Chowdhary 1
John Lillis 1
João Marques-Silva 1
Furshing Tsai 1
Debashri Roy 1
Debasis Mitra 1
Yunfeng Yang 1
El Bourennane 1
Michel Langevin 1
Rok Sosic 1
Thomas Schlichter 1
ChihDa Chien 1
Juichin Chu 1
Charles Alpert, 1
Andrew Huber 1
Jacopo Panerati 1
YiCheng Ho 1
Sanjiv Narayan 1
Hassan Ghasemzadeh 1
Matthias Kauer 1
William Lee 1
Srinivas Shakkottai 1
Yuan Xie 1
Le Zhang 1
Minsik Cho 1
Tsuyoshi Abe 1
Parthasarathi Dasgupta 1
Farid Najm 1
Yiping Fan 1
Pedro Morgado 1
Bo Liu 1
Pinhong Chen 1
Jeff White 1
Shakith Fernando 1
Adam Postula 1
Anuja Sehgal 1
Frank Hannig 1
Yu Cao 1
Karthik Shankar 1
Song Liu 1
Ge Yu 1
Javier Resano 1
Daniel Mozos 1
KuangCyun Hsiao 1
Dimin Niu 1
William Robinson 1
Lei Jiang 1
Brahim Al Farisi 1
James Harbin 1
Jason Higgins 1
Peter Marwedel 1
Saurabh Adya 1
Kiyin Chang 1
Ian Parberry 1
Chichou Kao 1
Heman Khanna 1
David Long 1
Mahesh Iyer 1
Yehia Massoud 1
Qingfeng Zhuge 1
Sunil Chappidi 1
Celina Val 1
Jongman Kim 1
Hyunggyu Lee 1
Jaume Abella 1
Sumit Mohanty 1
Gang Quan 1
CP Ravikumar 1
Yuwei Wu 1
Jay Roy 1
Nitin Chandrachoodan 1
Qingbo Wu 1
Dongha Jung 1
Stefanus Mantik 1
Puneet Gupta 1
Hai Lin 1
Vissarion Ferentinos 1
Erwan Raffin 1
Mark Yeary 1
Dennis Sylvester 1
Nakwoong Eum 1
Annette Bunker 1
Michael Birbas 1
Pierre Paulin 1
K Yuan 1
Alfredo Benso 1
James Huggins 1
Claudio Passerone 1
Chris Ostler 1
Gang Wang 1
Pengwen Chen 1
Chinchih Chang 1
Sudhanshu Vyas 1
Kai Huang 1
Alois Knoll 1
Guangyu Sun 1
Huazhong Yang 1
Chengyen Lin 1
Rensong Tsay 1
Zhiwei Qin 1
Maciek Kormicki 1
Xiaowei Li 1
Yuning Chang 1
Rajkumar Raval 1
Carl Pixley 1
Yang Xu 1
Libo Huang 1
Jongwon Lee 1
Rico Backasch 1
Gong Chen 1
Shigetoshi Nakatake 1
Chelun Hsu 1
Sungkwang Lee 1
Nima Darav 1
Xuandong Li 1
Malgorzata Marek-Sadowska 1
Sudheendra Kadri 1
Keesung Han 1
Hyunjik Song 1
Junhee Yoo 1
Hai Li 1
Georges Gielen 1
Shihyi Yuan 1
Joseph Demaio 1
Laurent Fournier 1
Wuan Kuo 1
Daniel Blakely 1
Reiner Hartenstein 1
Marco Sgroi 1
Narender Hanchate 1
Dannyziyi Chen 1
Christos Papachristou 1
Duo Li 1
Rainer Dömer 1
Lei Jiang 1
Hiroto Yasuura 1
Peng Yang 1
Trevor Hodges 1
I Tsai 1
David Landis 1
Maogang Wang 1
Incheol Park 1
Gernot Koch 1
Anand Sivasubramaniam 1
Fei Xia 1
Yenjen Chang 1
Yuke Wang 1
Rajib Nath 1
Wei Wang 1
Michael Tian 1
Riccardo Scarsi 1
Chihong Hwang 1
Charles Wen 1
Wim Meeus 1
Poyang Hsu 1
Jianbo Li 1
Debjit Pal 1
Vaughn Betz 1
Marc Renaudin 1
Fady Abouzeid 1
Bo Wang 1
Rajdeep Bondade 1
Naveed Sherwani 1
Yuchun Ma 1
Sheqin Dong 1
Shianling Wu 1
Karim Khordoc 1
Chiaheng Tu 1
Jiwon Hahn 1
Mahshid Roumi 1
Marie Flottes 1
Jiang Hu 1
Marc Geilen 1
Alex Jones 1
Aiman El-Maleh 1
Egor Sogomonyan 1
Wangqi Qiu 1
Zhuo Li 1
Suchismita Roy 1
Mingyung Ko 1
Suren Ramasubbu 1
Pokuan Huang 1
TzuTeng Lin 1
Michalis Galanis 1
Fernando Herrera 1
Paul Mesa 1
Sungchan Kim 1
Iyad Al Khatib 1
Rustam Nabiev 1
Daniel Casarotto 1
Peter Hawrylak 1
Jonathan Valamehr 1
Ted Huffmire 1
Yajun Ha 1
I Tseng 1
Amit Singh 1
Kiamal Pekmestzi 1
Vahid Lari 1
Ayse Coskun 1
Somsubhra Mondal 1
Qingxu Deng 1
Jean Legat 1
Gaurav Dhiman 1
Seyed Miremadi 1
Karel Heyse 1
Ali Mirtar 1
Chih Lin 1
Tao Feng 1
Syed Suhaib 1
Steven Bashford 1
Andrei Rădulescu 1
Geneeu Jan 1
András Orbán 1
Ernest Lampe 1
Ruth Bahar 1
Surendra Bommu 1
Richard Raimi 1
TzuYin Lin 1
Thanos Stouraitis 1
John Havlicek 1
MingChing Lu 1
Lipin Chang 1
Chifeng Li 1
Jeonghun Cho 1
ChiaoChen Fang 1
Upavan Gupta 1
Venkataraman Mahalingam 1
Ritayu Chen 1
Bernd Becker 1
Yuki Kobayashi 1
Masaharu Imai 1
Gerhard Dueck 1
David Miller 1
Fei He 1
Peter Vanbroekhoven 1
Jiliang Zhang 1
Eddie Cheng 1
Christian Buckl 1
Kamel Beznia 1
Franz Franchetti 1
Jun Matsushima 1
Shigeki Ohbayashi 1
Yumin Kuo 1
Érika Cota 1
Marcelo Lubaszewski 1
Andrew Kennings 1
Hongyu Chen 1
Pengchih Wang 1
Duo Liu 1
Nicolas Blanc 1
Rafael Rosales 1
William Song 1
Chen Huang 1
Joonho Kong 1
George Kornaros 1
Richard Lasslop 1
Jens Vygen 1
Qing Wu 1
M Joseph 1
John Jose 1
Yenpo Ho 1
Pohsun Wu 1
Haomo Tang 1
Yande Jiang 1
Takkei Lam 1
Charles Chiang 1
Walid Najjar 1
Partha Biswas 1
Bin Xiao 1
Jason Oberg 1
Baolei Mao 1
Anche Cheng 1
Sam Bayless 1
Seungcheol Baek 1
Chrysostomos Nicopoulos 1
Bojan Maric 1
Alexander Veidenbaum 1
Yier Jin 1
Shirshendu Das 1
Chieh Changfan 1
Huahsin Yeh 1
Jinkyu Koo 1
Hsiangyun Cheng 1
Hu Chen 1
Anupama Subramaniam 1
V Kamakoti 1
Seonwook Kim 1
Hai Zhou 1
Joseph Ganley 1
Martin Streubühr 1
Jens Gladigau 1
Michael Meredith 1
Brady Hunsaker 1
Juan Hamers 1
Chinghwa Cheng 1
Brett Meyer 1
Chunhan Chen 1
Yaoguang Wei 1
Cliff Sze 1
Andreas Burg 1
Seokhyun Lee 1
Harry Hoster 1
Dani Tannir 1
Bingsheng He 1
Marcela Zuluaga 1
Xing Hu 1
Yining Zhang 1
Shuangchen Li 1
Yokesh Kumar 1
Suganth Paul 1
Dimitris Bakalis 1
Fulvio Corno 1
Andy Lambrechts 1
Laleh Behjat 1
Fangming Ye 1
Srijan Kumar 1
Jaiming Lin 1
Ganapathy Parthasarathy 1
Smita Krishnaswamy 1
A Abbasian 1
Kyungsoo Lee 1
Mengchiou Wu 1
Seher Kiziltepe 1
Guanying Wu 1
Xubin He 1
Sunwook Kim 1
Seiji Kajihara 1
Michael Gössel 1
Weiping Shi 1
Xi Chen 1
Kohei Miyase 1
Lei Cheng 1
Paulo Centoducatte 1
Nicholas Callegari 1
Woochul Jeun 1
Youngjin Cho 1
José Gómez 1
Rance Rodrigues 1
Arunachalam Annamalai 1
Israel Koren 1
Yunghsiang Lu 1
Michael Henry 1
Jyothi Velamala 1
Xuehai Zhou 1
Chun Jason Xue 1
Kalyan Saladi 1
Mahadevan Ganapathi 1
Michael Moffitt 1
Philip Honsinger 1
Pedro Diniz 1
Zhiru Zhang 1
Montek Singh 1
Yuze Wu 1
Mineo Kaneko 1
Nikolaos Papandreou 1
Haralampos Pozidis 1
Andrew Walls 1
Siva Boga 1
Vassos Soteriou 1
Ngai Wong 1

Affiliation Paper Counts
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
Macau University of Science and Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
Huawei Technologies Co., Ltd. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
National Institute of Technology, Durgapur 1
Global Unichip 1
North China Electric Power University 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Microsoft Research 1
University of Potsdam 1
Beijing University of Chemical Technology 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of Central Florida 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Lancaster University 1
Oak Ridge National Laboratory 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers University 1
Nortel Networks 1
Institute of Computing Technology Chinese Academy of Sciences 1
Curtin University of Technology, Perth 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Gonzaga University 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
Lebanese American University 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Texas at San Antonio 1
University of Manchester 1
Universite de Bretagne-Sud 1
China National Petroleum Corporation 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
University of Kansas 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
University of Kaiserslautern 1
Nanjing University of Science and Technology 1
University of Kent 1
Auburn University 1
Oakland University 1
INRIA Rhone-Alpes 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Kwangwoon University 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Chengdu University of Information Technology 1
Washington State University Tri-Cities 1
National Taipei University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
Advanced Micro Devices, Inc. 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
East China Normal University 1
Villanova University 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Bar-Ilan University 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
University of Houston 2
Universitat Politecnica de Catalunya 2
CEA LETI 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
Silesian Polytechnic University, Gliwice 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Indian Institute of Technology, Guwahati 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
Michigan Technological University 2
University of Tubingen 2
Southern Methodist University 2
Washington State University Pullman 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Alcatel-Lucent 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institute for Research in IT and Random Systems 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
Indian Institute of Technology Roorkee 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
New York University Abu Dhabi 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Korea University 3
Bogazici University 3
Delft University of Technology 3
Kitakyushu University 3
The University of Hong Kong 3
Hong Kong University of Science and Technology 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
RWTH Aachen University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
New York University 3
Portland State University 3
Hanyang University 3
University of Brasilia 3
Stony Brook University 3
University of Melbourne 3
University of Pisa 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
Hunan University 3
University of Seville 3
University of Cyprus 3
NVIDIA 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
University of Electronic Science and Technology of China 4
Louisiana State University 4
Chung Hua University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Peking University 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Politecnico di Milano 4
Motorola 4
University of Cincinnati 4
Swiss Federal Institute of Technology, Zurich 4
Microsoft 4
IBM Austin Research Laboratory 4
University of Milan 4
Syracuse University 4
Universite de Rennes 1 4
Pohang University of Science and Technology 4
University of Dortmund 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
Western Michigan University 5
Royal Institute of Technology 5
University of Calgary 5
Instituto Superior Tecnico 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
National University of Singapore 5
University of Bristol 5
University of North Texas 5
Agilent Technologies 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Indian Institute of Technology, Delhi 5
Nanjing University 5
Fujitsu America, Inc. 5
Universite Grenoble Alpes 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
Zhejiang University 6
North Carolina State University 6
University of Illinois 6
Fudan University 6
Brown University 6
University of California, Davis 6
Holst Centre 6
Industrial Technology Research Institute of Taiwan 6
STMicroelectronics 6
National Taiwan University of Science and Technology 6
Swiss Federal Institute of Technology, Lausanne 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
Universidade de Lisboa 6
University of Minnesota System 7
Linkoping University 7
HP Labs 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
University of California, Santa Cruz 7
Shanghai Jiaotong University 7
State University of Campinas 7
Utah State University 7
University of Wisconsin Madison 7
McGill University 8
Iowa State University 8
Nanyang Technological University 8
Northwestern University 8
Federal University of Santa Catarina 8
University of Science and Technology of China 8
Indian Statistical Institute, Kolkata 8
Indian Institute of Technology, Madras 8
University of Bologna 8
Southern Illinois University at Carbondale 8
Karlsruhe Institute of Technology 8
Ulsan National Institute of Science and Technology 8
University of Michigan 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
University of Waterloo 9
Drexel University 9
Fuzhou University 9
Technical University of Munich 9
Freescale Semiconductor 9
University of Connecticut 9
National Central University Taiwan 9
University of Freiburg 9
University of Illinois at Chicago 9
The University of British Columbia 10
Yuan Ze University 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
National University of Defense Technology China 10
University of Utah 10
Broadcom Corporation 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
Chung Yuan Christian University 10
NEC Corporation 10
Princeton University 11
University of Massachusetts Amherst 11
Imperial College London 11
University of Notre Dame 11
University of Tehran 11
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
University of Florida 12
Korea Advanced Institute of Science & Technology 12
Samsung Electronics 13
University of Texas at Dallas 13
University of Patras 13
University of South Florida Tampa 14
Academia Sinica Taiwan 14
Catholic University of Leuven 14
Complutense University of Madrid 14
National Chung Cheng University 15
University of California, Berkeley 15
University of Southern California 15
University of Erlangen-Nuremberg 16
Chinese Academy of Sciences 16
University of Arizona 17
Pennsylvania State University 18
IBM 18
Cadence Design Systems 18
Ghent University 18
Virginia Tech 19
Arizona State University 20
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
University of California, Santa Barbara 21
Tsinghua University 24
National Cheng Kung University 25
University of Maryland 26
Eindhoven University of Technology 26
Chinese University of Hong Kong 28
Synopsys Incorporated 28
Duke University 30
Intel Corporation 31
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
University of Texas at Austin 35
Purdue University 36
University of Pittsburgh 37
Carnegie Mellon University 40
National Taiwan University 42
University of California, Riverside 43
University of California, San Diego 43
National Chiao Tung University Taiwan 44
Indian Institute of Technology, Kharagpur 45
Texas A and M University 51
University of California, Irvine 63
National Tsing Hua University 65
University of California, Los Angeles 65
Seoul National University 67

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
Archive


2016
Volume 21 Issue 3, July 2016 Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
Volume 22 Issue 1, June 2016  Issue-in-Progress
Volume 21 Issue 4, June 2016  Issue-in-Progress
Volume 21 Issue 2, January 2016

2015
Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Volume 20 Issue 3, June 2015
Volume 20 Issue 2, February 2015

2014
Volume 20 Issue 1, November 2014
Volume 19 Issue 4, August 2014
Volume 19 Issue 3, June 2014
Volume 19 Issue 2, March 2014

2013
Volume 19 Issue 1, December 2013
Volume 18 Issue 4, October 2013 Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Volume 18 Issue 3, July 2013
Volume 18 Issue 2, March 2013
Volume 18 Issue 1, January 2013 Special section on adaptive power management for energy and temperature-aware computing systems

2012
Volume 17 Issue 4, October 2012
Volume 17 Issue 3, June 2012 Special section on verification challenges in the concurrent world
Volume 17 Issue 2, April 2012
Volume 17 Issue 1, January 2012

2011
Volume 16 Issue 4, October 2011
Volume 16 Issue 3, June 2011
Volume 16 Issue 2, March 2011

2010
Volume 16 Issue 1, November 2010
Volume 15 Issue 4, September 2010
Volume 15 Issue 3, May 2010
Volume 15 Issue 2, February 2010

2009
Volume 15 Issue 1, December 2009
Volume 14 Issue 4, August 2009
Volume 14 Issue 3, May 2009
Volume 14 Issue 2, March 2009
Volume 14 Issue 1, January 2009

2008
Volume 13 Issue 4, September 2008
Volume 13 Issue 3, July 2008
Volume 13 Issue 2, April 2008
Volume 13 Issue 1, January 2008

2007
Volume 12 Issue 4, September 2007
Volume 12 Issue 3, August 2007
Volume 12 Issue 2, April 2007
Volume 12 Issue 1, January 2007

2006
Volume 11 Issue 4, October 2006
Volume 11 Issue 3, July 2006
Volume 11 Issue 2, April 2006
Volume 11 Issue 1, January 2006

2005
Volume 10 Issue 4, October 2005
Volume 10 Issue 3, July 2005
Volume 10 Issue 2, April 2005
Volume 10 Issue 1, January 2005

2004
Volume 9 Issue 4, October 2004
Volume 9 Issue 3, July 2004
Volume 9 Issue 2, April 2004
Volume 9 Issue 1, January 2004

2003
Volume 8 Issue 4, October 2003
Volume 8 Issue 3, July 2003
Volume 8 Issue 2, April 2003
Volume 8 Issue 1, January 2003

2002
Volume 7 Issue 4, October 2002
Volume 7 Issue 3, July 2002
Volume 7 Issue 2, April 2002
Volume 7 Issue 1, January 2002

2001
Volume 6 Issue 4, October 2001
Volume 6 Issue 3, July 2001
Volume 6 Issue 2, April 2001
Volume 6 Issue 1, Jan. 2001

2000
Volume 5 Issue 4, Oct. 2000
Volume 5 Issue 3, July 2000
Volume 5 Issue 2, April 2000
Volume 5 Issue 1, Jan. 2000

1999
Volume 4 Issue 4, Oct. 1999
Volume 4 Issue 3, July 1999
Volume 4 Issue 2, April 1999
Volume 4 Issue 1, Jan. 1999

1998
Volume 3 Issue 4, Oct. 1998
Volume 3 Issue 3, July 1998
Volume 3 Issue 2, April 1998
Volume 3 Issue 1, Jan. 1998

1997
Volume 2 Issue 4, Oct. 1997
Volume 2 Issue 3, July 1997
Volume 2 Issue 2, April 1997
Volume 2 Issue 1, Jan. 1997

1996
Volume 1 Issue 4, Oct. 1996
Volume 1 Issue 3, July 1996
Volume 1 Issue 2, April 1996
Volume 1 Issue 1, Jan. 1996
 
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