ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

H-Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs

In this article, we propose an efficient finite-element-based (FE-based) method for both steady and transient thermal analyses of high-performance... (more)


Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties... (more)

Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories

Constraint programming solvers, such as Satisfiability Modulo Theory (SMT) solvers, are capable tools in finding preferable configurations for... (more)

An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding

Due to limitations of cooling methods such as using fan and heat sink, dynamic thermal management... (more)


Performance isolation is critical in shared storage systems, a popular storage solution. In a shared storage system, interference between requests from different users can affect the accuracy of I/O cost accounting, resulting in poor performance isolation. Recently, NAND flash-memory-based solid-state drives (SSDs) have been increasingly used in... (more)

Accurate Analysis and Prediction of Enterprise Service-Level Performance

An enterprise service-level performance time series is a sequence of data points that quantify demand, throughput, average order-delivery time,... (more)

Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines

In recent years, dynamic program analysis (DPA) has been widely used in various fields such as... (more)

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology

Modern mobile processors integrating an increasing number of cores into one single chip demand... (more)

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

Future GPUs should have larger L2 caches based on the current trends in VLSI technology and GPU architectures toward increase of processing core... (more)

Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate... (more)


This article introduces a new approach to extreme static test compaction for functional test sequences that modifies the sequence in order to enhance the ability to omit test vectors from it and thus compact it. In the new approach, modification of the sequence and omission of test vectors from it are tightly coupled by focusing both subprocedures... (more)

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the... (more)


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ACM TODAES Special Section Call for Papers - IDEA: Integrating Dataflow, Embedded computing, and Architecture
- Special Section Guest Editors: Twan Basten (Eindhoven University of Technology), Orlando Moreira (Intel), Robert de Groote (Twente University) 
- Contact:

ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 25-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

Best Paper Award: Congratulations to Peter Milder, Franz Franchetti, James C. Hoe, and Markus Puschel on receiving the 2014 ACM TODAES Best Paper Award for their article titled Computer Generation of Hardware for Linear Digital Signal Processing Transforms, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 2, Article 15, April 2012.

Forthcoming Articles
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography

In this paper, we present a pairwise coloring (PWC) approach to tackle the layout decomposition problem for triple patterning lithography (TPL). The main idea is to reduce the problem to a set of bi-coloring problems. One obvious advantage of this method is that the existing double patterning lithography (DPL) techniques can be reused effortlessly. Any improvement on them can directly benefit the TPL counterpart. Moreover, we observe that each pass can be fulfilled efficiently by integrating an SPQR-tree graph division based bi-coloring method. In addition, to prevent the solution getting stuck in the local minima, an adaptive multi-start (AMS) approach is incorporated. Adaptive starting points are generated according to the vote of previous solutions. The experimental results show that compared with the two recently published works for TPL, the solution quality can be improved 43.7% and 15.1% on average respectively. Meanwhile, the runtime performance of our method is competitive with other methods.

Parallel Power Grid Analysis Based On Enlarged-Partitions

As the size and complexity of current VLSI circuits grows, faster power grid simulation is becoming more and more desirable. In this paper, we present a parallel iterative method for static VLSI power grid simulation. In the proposed enlarged-partition based preconditioned conjugate gradient (EPPCG) power grid solver, the power grid is divided into disjoint partitions that are subsequently enlarged to obtain accurate solution within each partition. The global solution obtained by solving enlarged partition problems concurrently acts as a highly effective parallel preconditioner. The combination of effective preconditioning and efficient parallelization helps achieve very high performance. The experiments show that our parallel implementation can achieve significant speed improvement [61X-142X] over a state-of-the-art direct solver.

A C2RTL framework supporting partition, parallelization and FIFO sizing for streaming applications

Developing circuits for streaming applications written in C (or its variants) can greatly benefit from C-to-RTL (C2RTL) synthesis. Yet, most existing C2RTL tools lack system-level options to trade off various design constraints, such as throughput and area. This paper proposes a hierarchical synthesis framework including automatic C-code partition, block-level parallelization and FIFO sizing. A mixed integer linear programming (MILP) approach is formulated to simultaneously find the optimal partition and block-level parallelization. Furthermore, a heuristic method is developed for large-scale problem instances. A FIFO sizing algorithm is introduced to determine the capacities of FIFOs that connect the blocks. Experimental results on seven real world applications demonstrate that the synthesis framework can effectively trade off various design constraints. Furthermore, the heuristic method achieves the optimal results in most cases with less than tenths of a second.

Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study

Phase-change memory (PCM) has several benefits including low cost, non-volatility, byte-addressability, etc., and limitations such as write endurance. There have been several hardware approaches to exploit the benefits while minimizing the negative impact of limitations. Software approaches could give further improvements, when used together with hardware approaches, by taking advantage of write behavior present in the program, e.g., write behavior on dynamically allocated data, which is hardly captured by hardware approaches. This work proposes a software design methodology to reduce costly PCM writes. First, on top of existing hardware approach such as Flip-N-Write, we advocate exploiting the capability of PCM bit-level differential write in the software by judiciously reusing previously allocated memory resource. In order to avoid wear-out incurred by the reuse, we present software-based wear-leveling methods which distribute writes across PCM cells. In order to further reduce PCM writes, we propose identifying data whose loss does not affect the functionality of the underlying software, and then diverting write traffic for those data items to volatile memory. To evaluate the effectiveness of these methods, as a case study, we applied the proposed methods to the design of journaling in SQLite which is an important database application commonly used in smartphones. For the experiments, we used an in-house PCM-based prototype board. Our experiments with four representative mobile applications show that the proposed design methods, which is applied on top of the hardware approach, Flip-N-Write, result in 75.2% further reduction in total bit updates in PCM, on average, without aggravating wear out compared with the baseline of PCM-based journaling which is based only on the hardware approach. Also, the proposed design methods result in 58.3% reduction in energy consumption and 31.7% reduction in runtime compared to the baseline design of SQLite journaling on Flash memory.

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM

Multi-level cell (MLC) phase-change RAM (PRAM) is expected to offer lower cost main memory than DRAM. However, poor write performance is one of the most critical problems for practical applications of MLC PRAM. In this paper, we present two schemes to improve write performance by controlling the target resistance distribution of MLC PRAM cells. First, we propose multiple RESET/SET operations which relax the target resistance bands of intermediate logic levels with additional RESET/SET operations, which reduces the program time of intermediate logic levels, thereby improving write performance. Second, we propose a two-step write scheme consisting of lightweight write and idle-time completion write that exploits the fact that hot dirty data tend to be overwritten in a short time period and the MLC PRAM often has long idle times. Experimental results show that the multiple RESET/SET and two-step write schemes result in an average IPC improvement of 15.1% and 10.7%, respectively, on a hybrid DRAM/PRAM main memory subsystem. Furthermore, their integrated solution results in an average IPC improvement of 22.7% (up to 46.3%).

Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms

Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, the energy-efficient computing is highly desired. In this paper, we focus on the energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments which can only be accessed by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintains the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments, and explore the multi-retention STT-RAM based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize the overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for the maximal energy savings. The experimental results show that our static technique reduces the cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows the strong capability in reducing the cache energy consumption by 85% with only 3% performance loss.

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs

Due to the inappropriate assignment of bump pads or the improper assignment of I/O buffers, the constructed buffered I/O signals in an area-I/O flip-chip design may yield the longer maximum delay. In this paper, the problem of assigning the performance-driven buffered I/O signals in an area-I/O flip-chip design is firstly formulated. Furthermore, the assignment of the buffered I/O signals can be divided into two sequential phases: performance-driven construction of I/O signals and timing-constrained assignment of I/O buffers. Finally, an efficient matching-based approach is proposed to construct the performance-driven I/O signals for the given I/O pins and assign the timing-constrained I/O buffers for the constructed I/O signals in the assignment of the buffered I/O signals in an area-I/O flip-chip design. Compared with Pengs SA-based approach on 7 tested circuits, the experimental results show that our proposed matching-based approach can further reduce 71.06% of the total path delay, 67.83% of the maximum input delay, 59.84% of the input skew, 68.87% of the maximum output delay and 61.846% of the output skew on the average by reconstructing the IO signals and reassigning the I/O buffers onto the I/O signals.

PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, e.g., in 14nm and below, where double patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches such as M2 and M3. Self-aligned double patterning (SADP) provides better control on the line edge roughness and overlay but it has very restrictive design constraints and prefers regular layout patterns. This paper presents a comprehensive pin access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include pre-computation of both intra-cell and inter-cell pin accessibility, as well as local and global pin access planning to enable the handshaking between standard cell level pin access and detailed routing under SADP constraints. Pin access driven rip- up and re-route scheme is further proposed to improve the ultimate routability. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

3D technology for networks-on-chip (NoCs) becomes attractive. It is important to present an effective scheme for 3D stacked NoC router and interconnect testing. A new approach to testing of NoC routers is proposed by classifying the routers. Routers with the same number of input/output ports fall into the same class. Routers of the same class are identical, whose tests are the same. A simple unicast-based multicast scheme is proposed to deliver test packets for the identical routers. It is found that the depth of the consumption buffer at each router has great impact on the test delivery time because test application and test delivery for router testing cannot be handled concurrently. Test delivery must set a router to the operational mode. A mathematical model is presented to evaluate the impact of consumption buffer depth on the test delivery time. A new and simple test application scheme is proposed for interconnect testing. Some interesting extensions are presented for further test time reduction and thermal consideration. Sufficient experimental results are presented by comparison with one previous method.

Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory

The increasing adoption of graphics processing units (GPUs) for high-performance computing raises the reliability challenge, which is generally ignored in traditional GPUs. GPUs usually support thousands of parallel threads and require a sizable register file. Such large register file is highly susceptible to soft errors and power-hungry. Although ECC has been adopted to register file in modern GPUs, it causes considerable power overhead, which further increases the power stress. Thus, an energy-efficient soft-error protection mechanism is more desirable. Besides its extremely low leakage power consumption, resistive memory (e.g. spin-transfer torque RAM) is also immune to the radiation induced soft errors due to its magnetic field based storage. In this paper, we propose to LEverage reSistive memory to enhance the Soft-error robustness and reduce the power consumption (LESS) of registers in the General-Purpose computing on GPUs (GPGPUs). Since resistive memory experiences longer write latency compared to SRAM, we explore the unique characteristics of GPGPU applications to obtain the win-win gains: achieving the near-full soft-error protection for the register file, and meanwhile substantially reducing the energy consumption with negligible performance loss. Our experimental results show that LESS is able to mitigate the registers soft-error vulnerability by 86% and achieve 61% energy savings with negligible (e.g. 1%) performance loss.

A New Uncertainty Budgeting Based Method for Robust Analog/Mixed-Signal Design

This article proposes a novel methodology for robust analog/mixed-signal IC design by introducing a notion of budget of uncertainty. This method employs a new conic uncertainty model to capture process variability and describes variability-affected circuit design as a set-based robust optimization problem. For a pre-specified yield requirement, the proposed method conducts uncertainty budgeting by associating performance yield with the size of uncertainty set for process variations. Hence the uncertainty budgeting problem can be further translated into a tractable robust optimization problem. Compared with the existing robust design flow based on ellipsoid model, this method is able to produce more reliable design solutions by allowing varying size of conic uncertainty set at different design points. In addition, the proposed method addresses the limitation that the size of ellipsoid model is calculated solely relying on the distribution of process parameters, while neglecting the dependence of circuit performance upon these design parameters. The proposed robust design framework has been verified on various analog/mixed-signal circuits to demonstrate its efficiency against ellipsoid model. An up to 24% reduction of design cost has been achieved by using the uncertainty budgeting based method.

A Finite-Point Method for Efficient Gate Characterization under Multiple Input Switching

DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors

In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real world applications. To effectively exploit these delay variations, we propose Dynamically Adaptable Resilient Pipeline (DARP)a series of runtime techniques to boost power performance efficiency and fault tolerance in a pipelined microprocessor. DARP employs early error prediction to avoid a major portion of the timing errors. We combine DARP with the state-of-art topologically homogeneous and power-performance heterogeneous (THPH) architecture to build up a new frontier of the energy-efficiency of multicore processor (DARP-MP). Using a rigorous circuit-architectural infrastructure, we demonstrate substantial improvements of DARP in the performance (9.420%) and energy efficiency (6.427.9%), compared to state-of-the-art techniques.While the energy-efficiency improvement of DARP-MP is 34.1% and 40.2%, compared against the original THPH, as well as another state-of-art multicore power-management scheme, respectively.

Complementary Synthesis for Encoder with Flow Control Mechanism

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing

Scan based testing is crucial to ensure correct functioning of chips. In this scheme, the scan and the capture phases interleave each other. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This paper proposes a new DFT scheme for Launch-On-Shift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing the CAD tools with extra search space for minimizing launch-to-capture switching activity through test pattern ordering (TPO). We go further and propose a new TPO algorithm that keeps track of the dont cares during the ordering process, so that the dont care filling step after the ordering process yields the best possible reduction in launch-to-capture switching activity. The proposed DFT assisted technique when applied to circuits in ITC99 benchmark suite, produced an average reduction of 17.68% in peak launch-to-capture switching activity (CSA) compared to the best known low power TPO technique. Even for circuits whose test cubes are not rich in dont care bits, the proposed technique produced an average reduction of 15% in peak CSA. While for the circuits with test cubes rich in dont care bits (e 75%) the average reduction is 24%. Interestingly, the proposed technique also reduces the power dissipation during scan phase by about 3.2% on an average.

Enhanced Test Compaction for Multi-Cycle Broadside Tests By Using State Complementation

Multi-cycle tests support test compaction by allowing each test to detect more target faults. The ability of multi-cycle broadside tests to provide test compaction depends on the ability of primary input sequences to take the circuit between pairs of states that are useful for detecting target faults. This ability can be enhanced by adding design-for-testability (DFT) logic that allows states to be complemented. This paper describes a test compaction procedure that uses such DFT logic to form a compact multi-cycle broadside test set for transition faults where the tests use constant primary input vectors. The use of complemented states also allows the procedure to increase the transition fault coverage beyond the transition fault coverage of a broadside test set. The procedure has the option of increasing the switching activity of the tests gradually in order to explore the tradeoff between the number of tests, the fault coverage, and the switching activity.

Design-for-Testability for Functional Broadside Tests under Primary Input Constraints

Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. When a circuit is embedded in a larger design, a functional broadside test needs to take into consideration the functional constraints that the design creates for its primary input vectors. At the same time, application of primary input vectors as part of a scan-based test requires hardware support. An earlier work considered the case where a primary input vector is held constant during a test. The approach described in this paper matches the hardware for applying primary input vectors to the functional constraints that the design creates. This increases the transition fault coverage that can be achieved by functional broadside tests. The paper also considers the effect on the transition fault coverage achievable using close-to-functional broadside tests.

Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements

An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems

This paper presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile for the specification and automatic generation of different components of Dynamic and Partially Reconfigurable Systems-on-Chip (SoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modelling and via model transformations, generating executable models which can be exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this paper are concerned with expediting the conception and implementation of the hardware platform and the integration of a safe and correct by construction reconfiguration controller. The paper builds upon previous research by integrating previously separated endeavors to obtain a complete PR system generation chain based on MDE techniques and tools, shielding the designer of many of the burdensome technological and too specific requirements. The methodology permits for the verification of the platform description at different stages in the development process (i.e. HDL for simulation, static FPGA implementation, controller simulation and verification) and to automatically generate the reconfigurable platform, enabling the designer using high-levels models to avoid the complexities associated with the design and implementation of PR systems (due mainly to a complex design flow and its associated tools). In order to demonstrate the benefits of the proposed approach, we present a case study in which we target the creation of an image processing application to be deployed into FPGA board; we present the required modelling strategies and we discuss how the compliation chains are integrated with the back-end Xilinx tools (the most mature version of PR technoilogy) to produce the necessary executable artifacts: VHDL for the platform description and a C description of the reconfiguration controller to be executed by an embedded processor.

Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) and hence lifetime of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically most critical. However, also the decoding stages can become aging-critical and limit the microprocessor lifetime, as we will show in this work. Therefore, we propose a novel aging-aware instruction set encoding methodology (ArISE), that improves the instruction encoding iteratively using a heuristic algorithm. In addition, the switching activities of the affected memory elements are considered in order to co-optimize lifetime and energy efficiency. Our experimental results show that MTTF of the decoding stages can be improved by 2.3x with negligible implementation costs.

Locality-Aware Network Utilization Balancing in NoCs

Hierarchical and multi-network networks-on-chip (NoCs) have been proposed in the literature to improve the energy- and performance-efficient scalability of the traditional flat-mesh NoC architecture. Theoretically, based on a small-world network based analysis, traditional hierarchical NoCs are expected to provide good scalability. However, the traditional theoretical analysis (e.g. for small-worldness) does not take into account the congestion phenomenon experienced in such networks. Counter intuitively, as shown in this work, breaking the hierarchy in traditional hierarchical NoCs and utilizing the proposed locality-aware network utilization (NU) balancing technique provides a better performance. This improvement in performance is observed through experimental analysis, which is contrasted with the theoretical analysis that does not account for congestion. In addition to the novelties for hierarchical networks, the application of the proposed locality-aware NU balancing scheme is extended to multi-network NoC topologies (with already separated networks). Results of the analysis show the superiority of applying the locality-aware NU balancing technique for a throughput and energy efficient scaling of the multi-network NoC architectures, much like those of the hierarchical NoCs. For instance, for a NoC with 1024 nodes the proposed NU balancing technique provides upto 95% higher throughput efficiency and consumes upto 29% lesser energy per flit compared to the best NoC topology without the NU balancing technique. The analysis also helps to render the choice of a NoC topology for traffic patterns varying in locality and non-locality on exa-scale computing CMPs.

Off-line Washing Schemes for Residue Removal in Digital Microfluidic Biochips

A digital microfluidic biochip (DMB) is often deployed for multiplexing several assays in space and in time. The residue left by one assay may contaminate the droplets used in the subsequent assays. Biochemical assays involving cell culture and those based on particle microfluidics also require sweeping of residual media from an active droplet on-chip. Thus, fluidic operations such as washing or residue removal are needed to be performed routinely either to clean contamination from the droplet pathways or for rinsing off certain droplets on the chip. In this work, several graph-based techniques are presented for off-line washing of biochips that may have either a regular geometry (e.g., a 2D array of electrodes), or an irregular geometry (e.g., an application-specific layout). The schemes can be used for total washing, i.e., for cleaning the entire biochip or for selective washing of sites or pathways located sparsely on the chip. The problem of reducing the path length and washing time of the droplets is investigated with or without capacity constraints. The contaminated pathways are assumed to be Manhattan or curved, and hence the proposed techniques are applicable to the conventional field-actuated DMBs as well as to the emerging class of light-actuated DMBs. These techniques will be useful in supporting the reliable operation of a wide class of emerging digital microfluidic healthcare devices.

Security-aware Obfuscated Priority Assignment for Automotive CAN Platforms

Security in automotive in-vehicle networks is an increasing problem with the growing connectivity of road vehicles. This paper proposes a security-aware scheduling for automotive CAN platforms with the aim of mitigating scaling effects of attacks on vehicle fleets. CAN is the dominating field bus in the automotive domain due to its simplicity, low cost, and robustness. While messages might be encrypted to enhance the security of CAN systems, schedules are usually identical for automotive platforms, comprising generally a large number of vehicle models. As a result, the identifier uniquely defines which message is sent, allowing attacks on a single vehicle to scale across a fleet of vehicles with the same platform. As a remedy, we propose a methodology that is capable of determining obfuscated message identifiers for individual vehicle schedules. Since identifiers directly represent message priorities, the approach has to take the resulting response time variations into account while satisfying application deadlines for each vehicle schedule separately. Our approach relies on QCQP solving in two stages, specifying first a set of feasible fixed priorities and subsequently bounded priorities for each message. With the obtained bounds, obfuscated schedules are determined, using a very fast randomized sampling. The experimental results, consisting of a large set of synthetic test cases and a realistic case study, give evidence of the efficiency of the proposed approach in terms of scalability. The results also show that the diversity of obtained schedules is effectively optimized with our approach, resulting in a very good obfuscation of CAN messages in in-vehicle communication.

Security-Aware Design Methodology and Optimization for Automotive Systems

In this paper, we propose a general security-aware design methodology to address security with other design constraints in a holistic framework and optimize design objectives. The novel methodology maps functional models to architectural platforms and explores security mechanism selection and architecture selection. It is applied to in-vehicle communications with the Controller Area Network (CAN) protocol and Time Division Multiple Access (TDMA) based protocols and Vehicle-to-Vehicle (V2V) communications with the Dedicated Short-Range Communication (DSCR) technology. We address both of security and safety requirements and propose efficient algorithms to solve the security-aware design problems. Experimental results demonstrate the effectiveness of our approach in system design without violating design constraints.

Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction

Array Size Computation under Uniform Overlapping & Irregular Accesses

The size required to store an array is crucial for an embedded system, as it affects the memory size, the energy per memory access and the overall system cost. Existing techniques for finding the minimum number of resources required to store an array are less efficient for codes with large loops and not regularly occurring memory accesses. They have to approximate the accessed parts of the array leading to overestimation of the required resources. Otherwise their exploration time is increased with an increase over the number of the different accessed parts of the array. We propose a methodology to compute the minimum resources required for storing an array which keeps the exploration time low and provides a near-optimal result for regularly and non-regularly occurring memory accesses and overlapping writes and reads.

Memory Management Scheme to Improve Utilization Efficiency and Provide Fast Contiguous Allocation without a Statically Reserved Area

Fast allocation of large blocks of physically contiguous memory plays a crucial role to boost the performance of multimedia applications in modern memory-constrained portable devices, e.g., smart phones, tablets, etc. Existing systems have addressed this issue by provisioning a large statically reserved memory area (SRA) in which only dedicated applications can allocate pages. However, this in turn degrades the performance of applications that are prohibited to utilize the SRA due to the reduced available memory pool. To overcome this drawback while maintaining the benefits of the SRA, we propose a new memory management scheme that uses a special memory region, called page-cache-preferred area (PCPA), in concert with a quick memory-reclaiming algorithm. The key of the proposed scheme is to enhance the memory utilization efficiency by enabling to allocate page-cached pages of all applications in the PCPA until pre-determined applications require to allocate big chunks of contiguous memory. At this point, clean page-cached pages in the PCPA are rapidly evicted without write-back to a secondary storage. Compared to the SRA scheme, experimental results show that the PCPA scheme can improve the throughput of memory- and IO-intensive applications by up to 92% while maintaining the performance of SRA-dedicated application.

Adapting to Varying Distribution of Unknown Response Bits

Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices until each device under test either fails or passes each test.With increasing process variations, the statistical diversity of manufactured devices is increasing, making such one-size-fits-all approaches increasingly inefficient. Adaptive test techniques address this problem by tailoring the test decisions for the statistical characteristics of the device under test. In this article, we present several adaptive strategies to enable adaptive unknown bit masking for faster-than-at speed testing so as to ensure no yield loss while attaining the maximum test quality based on tester memory constraints. We also develop a tester-enabled compression scheme that helps alleviate memory constraints further, shifting the trade-off space favorably to improve test quality.

Lowering Minimum Supply Voltage for Power Efficient Cache Design by Exploiting Data Redundancy

Voltage scaling is known to be an efficient way of saving systems power and energy, and large caches such as LLCs are good candidates to benefit from the voltage scaling considering their constantly increasing size. However, the Vccmin problem, that the lower bound of scalable voltage level is limited by process variation, is depriving the chance of the benefit. The lowering Vccmin incurs multi-bit faults, which cannot be efficiently resolved by current technologies due to their high complexity and power consumption. We overcame the limitation by exploiting data redundancy of memory hierarchy. For example, cache coherence states and several layers of cache organization naturally exposes the existence of redundancy of cache blocks. If blocks have redundant copies, their VCCMIN can be lowered; although faults happen on the blocks, they can be detected by relatively simpler ways than correction and recovered by reloading the redundant copies. Our scheme requires only minor modification to the existing cache design. We verified our idea on a cycle accurate simulator with SPLASH-2 and PARSEC benchmark suites, and found that VCCMIN of 2MB L2 cache can be further lowered by 0.1V in 32nm technology with negligible degradation in performance. As a result, we could reduce the power consumption by 28.2% on average at high failure rate of 10%.

A Cost Effective Energy Optimization Framework of Multi-core SoCs Based on Dynamically Reconfigurable Voltage-frequency Islands

Clock Period Minimization with Minimum Leakage Power

In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses gate downsizing (including higher threshold voltage assignment) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this paper considers the simultaneous application of buffer insertion and gate downsizing during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs

The key performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample-and-hold, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can be resulted from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high because both placement and routing problems are optimized simultaneously. This paper evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch M=0.695, the effective number of bits ENOB=8.314 bits, and the integral nonlinearity INL=0.816 LSB (least significant bits) for a 9-bit SAR ADC design.

Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling

Multicore platforms are increasingly used in real-time embedded applications. In the development of such applications, an efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and allowing savings in stack space. In this paper, we address the problem of mapping tasks to cores and assignment of the scheduling parameters for both partitioned Fixed-Priority and EDF scheduling algorithms with PTS. We formulate the optimization problems using Mixed Integer Linear Programming framework, and present a Simulated Annealing algorithm as well as an efficient heuristic algorithm as practical alternatives. We perform extensive performance evaluations using random synthetic tasksets and industrial case studies.

FuzzRoute: A Thermally Efficient Congestion Free Global Routing Method for Three Dimensional Integrated Circuits

The high density of interconnects, closer proximity of modules, and routing phase are pivotal during the layout of a performance centric three dimensional integrated circuit (3D IC). Heuristic based approaches are typically used to handle such NP complete problems of global routing in 3D ICs. To overcome the inherent limitations of deterministic approaches a novel methodology for multi-objective global routing based on fuzzy logic has been proposed in this paper. The guiding information generated after the placement phase is used during routing with the help of a Fuzzy Expert System to achieve thermally efficient and congestion free routing. A complete global routing solution is designed based on the proposed algorithms and the results are compared with selected fully-established global routers viz. Labyrinth, FastRoute3.0, NTHU-R, BoxRouter 2.0, and FGR. Experiments are performed over ISPD benchmarks. The proposed router called FuzzRoute achieves balanced superiority in terms of routability, runtime, and wirelength over others. The improvements on routing time for Labyrinth, BoxRouter 2.0, and FGR are 91.81%, 86.87%, and 32.16%, respectively. It may be noted that though FastRoute3.0 achieves fastest runtime, it fails to generate congestion free solutions for all benchmarks, which is overcome by the proposed FuzzRoute of the current paper. FuzzRoute also shows wirelength improvements of 17.35%, 2.88%, 2.44%, 2.83%, and 2.10% respectively over others.

ECDSA Passive Attacks, Leakage Sources and Common Design Mistakes

Elliptic Curves Cryptography (ECC) tends to replace RSA for public key cryptographic services. ECC is involved in many secure schemes such as Elliptic Curve Diffie-Hellman (ECDH) key agreement, Elliptic Curve Integrated Encryption Scheme (ECIES) and Elliptic Curve Digital Signature Algorithm (ECDSA). As for every cryptosystem, implementations of such schemes may jeopardize the inherent security provided by the mathematical properties of the ECC. Unfortunate implementation or algorithm choices may create serious vulnerabilities. The elliptic scalar operation is particularly sensitive in these schemes. This paper surveys passive attacks against well spread elliptic scalar algorithms highlighting leakage sources and common mistakes which can be used to attack the ECDSA scheme. Experimental results are provided to illustrate and demonstrate the effectiveness of each vulnerability. Finally, the paper describes the link between partial leakage and lattices attacks in order to understand and demonstrate the impact of small leakages on the security of ECDSA.

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference

Main memory latencies have become a major performance bottleneck for chip-multiprocessors (CMPs). Since reads are on the critical path, existing memory controllers prioritize reads over writes. However, writes must be eventually processed when the write queue is full. These writes are serviced in a burst to reduce the bus turnaround delay and increase the row-buffer locality. Unfortunately, a large number of reads may suffer long queuing delay when the burst-writes are serviced. The long write latency of future non-volatile memory will further exacerbate the long queuing delay of reads during burst-writes. In this paper, we propose a run-time mechanism, Adaptive Burst-Writes (ABW), to reduce the queuing delay of reads. Based on the row-buffer hit rate of writes and the arrival rate of reads, we dynamically control the number of writes serviced in a burst to trade off the write service time and the queuing latency of reads. For prompt adjustment, our history-based mechanism further terminates the burst-writes earlier when the row-buffer hit rate of writes in the previous burst-writes is low. As a result, our policy improves system throughput by up to 28% (average 10%) and 43% (average 14%) in CMPs with DRAM-based and PCM-based main memory.

Reliability-aware Resource Allocation and Binding in High Level Synthesis

Soft error is nowadays a major reliability issue for nanoscale VLSI, and addressing it during high level synthesis is essential to improve the efficiency of error mitigation. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables and operations have non-uniform soft error vulnerabilities, we propose a novel reliability-aware allocation and binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive vulnerability analysis at the behavioral level by considering error propagation and masking in both control and data flows. Then the optimizations based on integer linear programming, as well as heuristic algorithm, are employed to incorporate the behavioral vulnerabilities into the register and functional unit binding phases to achieve cost-efficient error mitigation. The experimental results reveal that compared with the previous techniques which ignored behavioral vulnerabilities, the proposed approach can achieve up to 85% reliability improvement with the same amount of area budget in the RTL design.

TSocket: Thermal Sustainable Power Budgeting

As technology scales, thermal management for multi-core architectures becomes a critical challenge due to increasing power density and higher integration density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core configurations. In multi-core era, a chip-wide power budget, however, is not sufficient to ensure thermal constraints because the thermal sustainable power capacity varies with different threading strategies and core configurations. In this paper, we propose two models to estimate the thermal sustainable power capacity dynamically: homogeneous power model and heterogeneous power model. These two models convert the thermal effect of threading strategies and core configurations into power capacity, which provide a context-based power core budget for the power budgeting. Based on these models, we introduce a power budgeting framework aiming to optimize the performance within thermal constraints, named as TSocket. Compared to the chip-wide power budgeting solution, TSocket shows 19% of performance improvement for the PARSEC benchmarks in single program scenario and 9.5%performance improvement in multi-program scenario. The performance improvement is achieved by reducing thermal violations and providing extra power budget.

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions

In this paper, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycle for the CFU and clock period extension for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication test, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violation is prevented, and hence, all the manufactured extensible processors work with a predefined clock cycle time. In addition, to study the effect of the objective function (used during the selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps improving the speedup further. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of the conventional approaches.


Publication Years 1996-2015
Publication Count 789
Citation Count 3743
Available for Download 789
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First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Fellows (2013)
ACM Distinguished Member (2008)
ACM Senior Member (2006)
Jason Cong ACM Fellows (2008)
Giovanni DeMicheli ACM Fellows (2001)
Srinivas Devadas ACM Fellows (2014)
Nikil D. Dutt ACM Fellows (2014)
ACM Distinguished Member (2007)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
W. Kent Fuchs ACM Fellows (2000)
Ronald L. Graham ACM Fellows (1999)
Rajiv Gupta ACM Fellows (2009)
Matthew Guthaus ACM Senior Member (2013)
John P Hayes ACM Fellows (2001)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
ACM Fellows (1996)
Andrew Kahng ACM Fellows (2012)
Sung Mo Kang ACM Fellows (2001)
Kenneth W Kennedy ACM Fellows (1995)
John Lee ACM Senior Member (2014)
Sharad Malik ACM Fellows (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM - IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Krishna Palem ACM Fellows (2005)
Ian Parberry ACM Distinguished Member (2015)
Janak H Patel ACM Fellows (2001)
Massoud Pedram ACM Distinguished Member (2008)
Martha Pollack ACM Fellows (2011)
Dhiraj Pradhan ACM Fellows (1999)
Viktor Prasanna ACM Fellows (2007)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM - IEEE CS Eckert-Mauchly Award (2002)
ACM Fellows (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
ACM Fellows (1996)
Karem Sakallah ACM Fellows (2012)
Alberto Luigi Sangiovanni Vincentelli ACM Fellows (2014)
Robert Schreiber ACM Fellows (2012)
ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Donald E Thomas ACM Fellows (2007)
Mateo Valero ACM Distinguished Service Award (2012)
ACM - IEEE CS Eckert-Mauchly Award (2007)
ACM Fellows (2002)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Marilyn Claire Wolf ACM Fellows (2001)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 16
Nikil Dutt 15
Jason Cong 12
Irith Pomeranz 10
Krishnendu Chakrabarty 10
Tingting Hwang 9
Sachin Sapatnekar 9
Partha Chakrabarti 9
Lei He 8
Sheldon Tan 8
Yaowen Chang 8
Frank Vahid 7
Pallab Dasgupta 7
Danny Wong 7
Luca Benini 7
Spyros Tragoudas 6
Alexandru Nicolau 6
Martin Wong 6
Taewhan Kim 6
Yunheung Paek 6
John Hayes 6
Ryan Kastner 6
Igor Markov 6
Radu Marculescu 6
Sudhakar Reddy 6
Ali Dasdan 5
Sharad Malik 5
Jenqkuen Lee 5
Mahmut Kandemir 5
Umit Ogras 5
Kiyoung Choi 5
Kaushik Roy 5
Aviral Shrivastava 5
Rajeev Kumar 5
Giovanni De Micheli 5
Tony Givargis 5
Nagarajan Ranganathan 5
Andrew Kahng 5
Chengkok Koh 5
Roman Lysecky 5
Massoud Pedram 5
Chungkuan Cheng 5
Jingyang Jou 4
Sunil Khatri 4
Kwangting Cheng 4
Rajesh Gupta 4
Zijiang Yang 4
El Aboulhamid 4
Evangeline Young 4
Aarti Gupta 4
Xiaobosharon Hu 4
Pinghung Yuh 4
Peter Petrov 4
Hungming Chen 4
Alex Jones 4
Bhargab Bhattacharya 4
Sunyuan Hsieh 4
Hans Wunderlich 4
Naehyuck Chang 4
Chang Liu 4
Allen Wu 4
Miodrag Potkonjak 4
Preeti Panda 4
Jongeun Lee 4
Dinesh Mehta 4
Hai Zhou 4
Franco Fummi 4
Paulo Flores 4
Dirk Stroobandt 4
Yuchin Hsu 3
Xiaoyu Song 3
Yunsi Fei 3
Paul Gratz 3
Shiyu Huang 3
Chenjie Yu 3
Arnout Vandecappelle 3
Peter Cheung 3
Karem Sakallah 3
Chungwen Huang 3
Azadeh Davoodi 3
Fadi Kurdahi 3
Sarma Vrudhula 3
Gianpiero Cabodi 3
Massimo Poncino 3
Pai Chou 3
Juan Maestro 3
Partha Roop 3
Seongnam Kwon 3
Soheil Ghiasi 3
Kurt Keutzer 3
Thambipillai Srikanthan 3
Majid Sarrafzadeh 3
Xiangrong Zhou 3
Martin Palkovič 3
Pedro Reviriego 3
Daniel Gajski 3
Madhu Mutyam 3
David Atienza 3
Janak Patel 3
Per Kjeldsberg 3
José Monteiro 3
Chialin Yang 3
Ankur Srivastava 3
Chiuwing Sham 3
Nicholas Zamora 3
Enrico Macii 3
Yiping You 3
Edwin Sha 3
Sule Ozev 3
Elizabeth Rudnick 3
Saojie Chen 3
Shuvra Bhattacharyya 3
Hai Wang 3
Priyank Kalla 3
Seda Memik 3
George Constantinides 3
Iris Jiang 3
Shihchieh Chang 3
Waikei Mak 3
Twan Basten 3
Shihhsu Huang 3
Hao Yu 3
Peng Li 3
Xianlong Hong 3
Greg Stitt 3
Chakkuen Wong 3
Li Wang 3
Krishnendu Chakrabarty 3
Dimitrios Kagaris 3
Diana Marculescu 3
Henk Corporaal 3
Praveen Raghavan 3
Karel Bruneel 3
Soonhoi Ha 3
Ramesh Karri 3
Valeria Bertacco 3
Yuanhao Chang 3
Viktor Prasanna 3
Paolo Prinetto 3
Jintai Yan 3
Paoann Hsiung 3
Sreejit Chakravarty 3
Axel Jantsch 3
Wen Jone 3
Guangming Wu 3
Ozcan Ozturk 3
Sisira Panda 3
Zoran Salcic 3
Dipankar Das 3
Masanori Kurimoto 3
Gary Dispoto 2
Yuliang Wu 2
Yinhe Han 2
Jun Yang 2
Joann Paul 2
Sergio Nocco 2
Konstantin Moiseev 2
Chingren Lee 2
Swapna Dontharaju 2
Kees Goossens 2
Chinhsien Wu 2
Chao Wang 2
Meikang Qiu 2
David Pan 2
Masato Edahiro 2
Aiqun Cao 2
Qing Duan 2
Jos Huisken 2
Chiaming Chang 2
Donald Thomas 2
Hsinhung Chen 2
Ronald Blanton 2
S Ramesh 2
Guido Araújo 2
Matteo Reorda 2
Fei Su 2
Wayne Luk 2
P Chakrabarti 2
Francesco Poletti 2
Julien Schmaltz 2
Miguel Miranda 2
Matthew Guthaus 2
Gustavo Wilke 2
Doosan Cho 2
James Cain 2
Leonid Mats 2
Marco Bekooij 2
Franjo Ivančić 2
Yowtyng Nieh 2
Maurizio Rebaudengo 2
Russell Tessier 2
Kiwook Kim 2
Kyumyung Choi 2
Robert Walker 2
Janming Ho 2
Sujit Dey 2
Srinivas Devadas 2
Vigyan Singhal 2
Ismail Kadayif 2
Deepak Mathaikutty 2
Levent Aksoy 2
Srinivas Katkoori 2
Maria Michael 2
Smita Bakshi 2
Siddhartha Mukhopadhyay 2
Qinru Qiu 2
Rudy Lauwereins 2
Mohammad Arjomand 2
Andreas Dandalis 2
Yi Wang 2
Bo Zhao 2
Sudhakar Yalamanchili 2
Jagannathan Ramanujam 2
Natarajan Viswanathan 2
Román Hermida 2
Christophe Wolinski 2
Baris Taskin 2
Alper Sen 2
Yongjoo Kim 2
Wim Heirman 2
Dimitrios Soudris 2
Zebo Peng 2
Chiachun Tsai 2
Erik Brockmeyer 2
Inki Hong 2
Duncan Walker 2
Dong Xiang 2
Masahiro Fujita 2
Farinaz Koushanfar 2
Naiwen Chang 2
Sivaram Gopalakrishnan 2
Bocheng Lai 2
Elaheh Bozorgzadeh 2
Mehrdad Nourani 2
Chunjason Xue 2
Saraju Mohanty 2
Željko Žilić 2
Xiaoping Hu 2
Marco Murciano 2
Stefano Quer 2
Tajana Rosing 2
Zonghua Gu 2
Eduard Cerny 2
Jun Gu 2
Poyuan Chen 2
Junji Sakai 2
Abhijit Jas 2
Sungmo Kang 2
Roberto Passerone 2
Luciano Lavagno 2
Michel Auguin 2
Michael Hsiao 2
Min Xu 2
Luigi Carro 2
Chiajui Hsu 2
José Pino 2
Jun Yang 2
Xuexin Liu 2
Anmol Mathur 2
Freek Verbeek 2
Zhiyu Zeng 2
Dongsheng Ma 2
Jochen Jess 2
Akash Kumar 2
Leyla Nazhandali 2
Jun Zeng 2
Teiwei Kuo 2
Timothy Sherwood 2
Marc Boulé 2
Guangyu Chen 2
Siddharth Garg 2
Arnab Roy 2
Shihhao Hung 2
Steven Wilton 2
Wayne Wolf 2
Graziano Pravadelli 2
John Gough 2
Avinash Malik 2
Jörg Henkel 2
Swarup Bhunia 2
Susmita Sur-Kolay 2
Ricardo Reis 2
Paul Thadikaran 2
Yiyu Shi 2
C Shi 2
Younlong Lin 2
Puneet Gupta 2
Laungterng Wang 2
Jiping Liu 2
Nicola Bombieri 2
Yuan Xie 2
Hui Liu 2
Guihai Yan 2
Zili Shao 2
Jürgen Teich 2
Junjuan Xu 2
Alberto Sangiovanni-Vincentelli 2
Melvin Breuer 2
Kai Zhu 2
ChengHsing Yang 2
Manfred Glesner 2
Adnan Aziz 2
Nur Touba 2
Tsungyi Ho 2
Ranga Vemuri 2
Shantanu Dutt 2
Michael Riepe 2
Mohammad Tehranipoor 2
Magdy Abadir 2
Hongbing Fan 2
Jim Holt 2
Hyesoon Kim 2
Muhammet Ozdal 2
Avinoam Kolodny 2
Ansuman Banerjee 2
Marlin Mickle 2
Hiroaki Inoue 2
Kanupriya Gulati 2
Luís Silveira 2
Yiyu Liu 2
Deming Chen 2
José Mendías 2
Ronald Graham 2
Prabhat Mishra 2
M Balakrishnan 2
Guy Gogniat 2
Stan Liao 2
Erik Marinissen 2
Mike Lee 2
B Rau 2
Meeta Srivastav 2
Sreeranga Rajan 2
Michael Kochte 2
Bart Mesman 2
Anna Bernasconi 2
Xin Yuan 2
Bin Liu 2
Shmuel Wimer 2
Shenchih Tung 2
Dawei Chang 2
Mario López 2
Arcot Sowmya 2
Rajdeep Mukhopadhyay 2
Peichen Pan 2
Chung Tsao 2
Murali Jayapala 2
Javed Absar 2
Youngsoo Shin 2
Lei Li 2
Krzysztof Kuchcinski 2
Yvon Savaria 2
Sandeep Shukla 2
Costas Goutis 2
Kaihui Chang 2
Peng Li 2
Rafal Baranowski 2
Valentina Ciriani 2
Pochun Huang 2
Jingyang Jou 2
Rina Panigrahy 1
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Tianshi Chen 1
Olivier Temam 1
Salvador Mir 1
Xing Huang 1
Hao Li 1
Vijay Sundararajan 1
Juan Lanchares 1
Rajiv Gupta 1
Jian Liu 1
Qi Zhang 1
Zili Shao 1
Koen Van Eijk 1
Qin Zhao 1
E Mariatos 1
Hsinhung Lin 1
Yoshiaki Fukui 1
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Young Cho 1
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Paul Chau 1
Pai Chou 1
Saket Gupta 1
Sartaj Sahni 1
Koushik Chakraborty 1
Vilasita Kuntamukkala 1
Jiang Hu 1
Anjur Krishnakumar 1
Sotirios Xydis 1
George Economakos 1
Nicholas Imbriglia 1
Giovanni De Micheli 1
Sherief Reda 1
Jin Sun 1
Takeshi Yamamoto 1
Satoshi Nakano 1
John Lee 1
Ahmad Al-Yamani 1
Steve Tjiang 1
Nagu Dhanwada 1
Andrew Cassidy 1
Hua Xiang 1
Xiaoqing Wen 1
Xiaoqing Yang 1
Yuliang Wu 1
Bert Geelen 1
Jaehyun Kim 1
Rajeev Rao 1
Dinesh Ramanathan 1
David Van Campenhout 1
Hussain Al-Asaad 1
Jonathan Martin 1
Arijit Mondal 1
Xijiang Lin 1
Jie Gong 1
Les Walczowski 1
Dilvan Moreira 1
Antara Ain 1
Venkat Thanvantri 1
Andrew DeOrio 1
Shangping Ren 1
J Van Eijnhoven 1
Moritz Schmid 1
Sandip Kundu 1
Ryan Cochran 1
Atsuto Hanami 1
Juyueh Lee 1
Weifeng He 1
Zainalabedin Navabi 1
David Berner 1
Calin Ciordas 1
Alex Doboli 1
Hai Lin 1
Chungki Oh 1
Jingqing Mu 1
Mengchen Wu 1
Richard Brown 1
Kiseok Chung 1
Erik D'Hollander 1
Michel Renovell 1
Juergen Schloeffel 1
Yaping Lin 1
Lu Sha 1
Mottaqiallah Taouil 1
Gang Chen 1
Reinhardt Euler 1
Sandip Das 1
Ganesh Gopalakrishnan 1
LiehMing Wu 1
Hasan Arslan 1
Haibo Wang 1
Chuanjun Zhang 1
Farshad Firouzi 1
Tian Zhang 1
Fahimeh Jafari 1
Tomvander Aa 1
Savithri Sundareswaran 1
Mark Johnson 1
Stefan Pees 1
Heinrich Meyr 1
Alexios Birbas 1

Affiliation Paper Counts
FZI Research Computer Science Research Center Karlsruhe 1
Asyst Technologies, Inc. 1
King Abdullah University of Science and Technology 1
Zenasis Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
International Institute of Information Technology, Kolkata 1
Barcelona Supercomputing Center 1
Hitachi America, Ltd. 1
STMicroelectronics Ltd - Bristol 1
National Pingtung Institute of Commerce 1
Faraday Technology Corporation 1
Universite de Lyon 1
Intel Development Center, Israel 1
Toshiba America Research, Inc 1
Universite de Strasbourg 1
Global Unichip 1
New York University Abu Dhabi 1
University of Potsdam 1
New York University 1
University of Virginia 1
Indian Institute of Technology, Kanpur 1
University of New Orleans 1
National Chi Nan University 1
Chongqing University 1
Ecole Centrale Marseille 1
National Taiwan Ocean University 1
Missouri University of Science and Technology 1
University of Maryland, Baltimore County 1
The University of North Carolina at Chapel Hill 1
Northrop Grumman corporation 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Valparaiso University 1
University of Udine 1
Clarkson University 1
University of Nebraska - Lincoln 1
Royal Military College of Canada 1
Nokia 1
School of Higher Technology - University of Quebec 1
San Francisco State University 1
Oracle Corporation 1
NXP Semiconductors 1
National Ilan University Taiwan 1
St. Louis University 1
Siemens AG 1
Daegu University 1
Wuhan University 1
Karlsruhe Institute of Technology, Campus South 1
Kent State University 1
Texas State University-San Marcos 1
Rutgers University 1
Nortel Networks 1
Curtin University of Technology, Perth 1
Indian Institute of Technology Roorkee 1
McMaster University 1
University at Buffalo, State University of New York 1
University of Akron 1
University of Texas System 1
North Dakota State University 1
University of Bridgeport 1
Miami University Oxford 1
Griffith University 1
Naval Postgraduate School 1
Concordia University, Montreal 1
Federal University of Santa Maria 1
University of Idaho 1
Texas Instruments (India) Ltd 1
Lahore University of Management Sciences 1
Hynix Semiconductor Inc. 1
P. A. College of Engineering 1
International Medical Equipment Collaborative 1
Indian Institute of Management Calcutta 1
Macronix International Co 1
Nan-Tai Institute of Technology 1
Winbond Electronics Corporation 1
Kung Shan Institute of Technology 1
DoCoMo Communications Laboratories Europe GmbH 1
Yahoo Inc. 1
Institute for Information Industry Taiwan 1
Synopsys (India) Pvt. Ltd. 1
Mindspeed Technologies 1
University of Colorado at Boulder 1
Wilfrid Laurier University 1
Mississippi State University 1
Florida State University 1
France Telecom 1
University of Calgary 1
University of Texas at San Antonio 1
Universite de Bretagne-Sud 1
University of Ioannina 1
Fu Jen Catholic University 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Ecole Normale Superieure de Lyon 1
Google Inc. 1
City University of New York 1
Lawrence Berkeley National Laboratory 1
Thomson, SA 1
Cornell University 1
Commissariat a L'Energie Atomique CEA 1
Hong Kong University of Science and Technology 1
Colorado State University 1
Silicon Graphics, Inc. 1
Tampere University of Technology 1
University of St. Thomas, Minnesota 1
Fudan University 1
University of Kaiserslautern 1
University of Kent 1
Auburn University 1
Oakland University 1
Qualcomm Incorporated 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Indian Institute of Technology, Bombay 1
Providence University Taiwan 1
Oxford Brookes University 1
Peking University 1
Kettering University 1
University of Southern California, Information Sciences Institute 1
University of Washington 1
University of Washington Seattle 1
North Carolina Agricultural and Technical State University 1
Robert Bosch GmbH 1
University of Trento 1
Washington State University Tri-Cities 1
National Taipei University 1
Michigan Technological University 1
University of New Brunswick 1
The University of North Carolina System 1
Vienna University of Technology 1
University of South Carolina 1
Sogang University 1
Technical University of Dresden 1
Bowling Green State University 1
LSI Corporation 1
Taiwan Semiconductor Manufacturing Company 1
Memorial University of Newfoundland 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
Air Force Research Laboratory 1
Boston University 1
State University of Rio Grande do Sul 1
United States Air Force Institute of Technology 1
University of Twente 1
Russian Academy of Sciences 1
Bahcesehir University 1
Catholic University of Pelotas 1
Microsoft Research 1
Villanova University 2
University of Lisbon 2
Virginia Commonwealth University 2
Polytechnic University - Brooklyn 2
Hefei University of Technology 2
Illinois Institute of Technology 2
Vanderbilt University 2
Mentor Graphics Corporation 2
Feng Chia University 2
Universitat Politecnica de Catalunya 2
Altera Corporation 2
CNRS Centre National de la Recherche Scientifique 2
King Fahd University of Petroleum and Minerals 2
Xilinx Inc. 2
Washington University in St. Louis 2
Kyushu University 2
IBM Research 2
National Sun Yat-Sen University Taiwan 2
Japan Advanced Institute of Science and Technology 2
National Taipei University of Technology 2
Beihang University 2
Brno University of Technology 2
University of Cantabria 2
University of Denver 2
University of York 2
Radboud University Nijmegen 2
University of Tubingen 2
Southern Methodist University 2
Wright State University 2
George Mason University 2
Binghamton University State University of New York 2
Technical University of Crete 2
Osaka University 2
Southern Illinois University 2
Open University of the Netherlands 2
University of Ferrara 2
University of Lethbridge 2
Hanyang University 2
University of Southampton 2
University of Tokyo 2
Xidian University 2
Swiss Federal Institute of Technology, Zurich 2
Alcatel-Lucent 2
Stony Brook University 2
Universidad Autonoma de Madrid 2
University of Oxford 2
Institut de Recherche en Informatique et Systemes Aleatoires 2
University of Pisa 2
Lund University 2
National Semiconductor Corporation 2
Columbia University 2
Universite d' Evry Val d'Essonne 2
Infineon Technologies AG 2
Democritus University of Thrace 2
University of Queensland 2
Michigan State University 2
American University of Beirut 2
Cyprus University of Technology 2
National Key Laboratory for Parallel and Distributed Processing 2
Realtek Semiconductor Corp. 2
Avant Corporation 2
Universite Grenoble Alpes 2
Case Western Reserve University 3
Catholic University of Louvain 3
Electronics Telecommunication Research Institute 3
University of Victoria 3
University of Arkansas - Fayetteville 3
Instituto Superior Tecnico 3
University of Electronic Science and Technology of China 3
Bogazici University 3
Delft University of Technology 3
The University of Hong Kong 3
Chung Hua University 3
University of Catania 3
University of Dublin, Trinity College 3
Bilkent University 3
RWTH Aachen University 3
Universite de Bretagne Occidentale 3
Hewlett-Packard 3
Tunghai University 3
Portland State University 3
University of Brasilia 3
University of Melbourne 3
Cisco Systems 3
Budapest University of Technology and Economics 3
University of Milan 3
Universite de Rennes 1 3
University of Oklahoma 3
University of California System 3
Northeastern University China 3
Hunan University 3
University of Seville 3
University of Cyprus 3
Karlsruhe Institute of Technology 3
Sunchon National University 4
National Technical University of Athens 4
TIMA Laboratoire 4
Zhejiang University 4
Northwestern Polytechnical University China 4
University College Dublin 4
Motorola Austin 4
Louisiana State University 4
Renesas Technology Corporation 4
City University of Hong Kong 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Industrial Technology Research Institute of Taiwan 4
Politecnico di Milano 4
University of North Texas 4
Motorola 4
University of Cincinnati 4
Microsoft 4
IBM Austin Research Laboratory 4
Syracuse University 4
Utah State University 4
University of Dortmund 4
Ulsan National Institute of Science and Technology 4
Western Michigan University 5
Royal Institute of Technology 5
North Carolina State University 5
Rice University 5
Technical University of Darmstadt 5
Norwegian University of Science and Technology 5
Texas Instruments 5
University of Tennessee Space Institute 5
Philips Research 5
National University of Singapore 5
Fuzhou University 5
University of Bristol 5
National University of Defense Technology China 5
Agilent Technologies 5
Shanghai Jiaotong University 5
Swiss Federal Institute of Technology, Lausanne 5
University of New South Wales 5
Technical University of Madrid 5
IBM Zurich Research Laboratory 5
Kyushu Institute of Technology 5
Indian Institute of Technology, Delhi 5
Nanjing University 5
Fujitsu America, Inc. 5
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 6
University of Illinois 6
Nanyang Technological University 6
Brown University 6
Technical University of Lisbon 6
University of California, Davis 6
Holst Centre 6
University of Connecticut 6
STMicroelectronics 6
Indian Institute of Technology, Madras 6
National Taiwan University of Science and Technology 6
University of Bologna 6
Northeastern University 6
University of Verona 6
Universite Nice Sophia Antipolis 6
Magma Design Automation, Inc. 6
Nebrija University 6
McGill University 7
University of Minnesota System 7
Northwestern University 7
Linkoping University 7
HP Labs 7
University of Florida 7
Drexel University 7
IBM Thomas J. Watson Research Center 7
National Chung Hsing University 7
Polytechnic School of Montreal 7
Technical University of Munich 7
Massachusetts Institute of Technology 7
Technion - Israel Institute of Technology 7
National Central University Taiwan 7
University of California, Santa Cruz 7
Indian Statistical Institute, Kolkata 7
State University of Campinas 7
University of Wisconsin Madison 7
Iowa State University 8
University of Waterloo 8
Federal University of Santa Catarina 8
University of Science and Technology of China 8
University of Notre Dame 8
University of Tehran 8
University of Utah 8
Broadcom Corporation 8
Southern Illinois University at Carbondale 8
Chung Yuan Christian University 8
University of Michigan 9
Samsung Electronics 9
University of Auckland 9
University of Bonn 9
University of Montreal 9
Stanford University 9
Freescale Semiconductor 9
University of Freiburg 9
University of Illinois at Chicago 9
Princeton University 10
The University of British Columbia 10
Yuan Ze University 10
University of Stuttgart 10
NEC Laboratories America, Inc. 10
University of Iowa 10
Sharif University of Technology 10
University of Minnesota Twin Cities 10
NEC Corporation 10
Korea Advanced Institute of Science & Technology 10
University of Massachusetts Amherst 11
Imperial College London 11
University of Patras 11
Federal University of Rio Grande do Sul 12
Hong Kong Polytechnic University 12
Academia Sinica Taiwan 12
University of Texas at Dallas 13
University of California, Berkeley 13
Catholic University of Leuven 13
University of Southern California 13
University of South Florida Tampa 14
National Chung Cheng University 14
Chinese Academy of Sciences 14
Complutense University of Madrid 14
University of Arizona 15
University of Erlangen-Nuremberg 16
Pennsylvania State University 16
Arizona State University 16
IBM 18
Tsinghua University 18
Virginia Tech 18
Cadence Design Systems 18
University of California, Santa Barbara 18
Ghent University 18
Chinese University of Hong Kong 19
Georgia Institute of Technology 20
University of Illinois at Urbana-Champaign 21
National Cheng Kung University 23
University of Maryland 26
Eindhoven University of Technology 26
Duke University 27
Synopsys Incorporated 28
University of Texas at Austin 28
Purdue University 30
Intel Corporation 30
Interuniversity Micro-Electronics Center at Leuven 31
University Michigan Ann Arbor 32
Polytechnic Institute of Turin 34
Carnegie Mellon University 35
University of Pittsburgh 36
University of California, Riverside 37
National Taiwan University 40
National Chiao Tung University Taiwan 41
Texas A and M University 42
University of California, San Diego 43
Indian Institute of Technology, Kharagpur 45
Seoul National University 59
University of California, Irvine 63
National Tsing Hua University 63
University of California, Los Angeles 65

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems

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