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A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
This article describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed...
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
Kevin M. Lepak, Min Xu, Jun Chen, Lei He
In this article, we first show that existing net ordering formulations to minimize noise are no longer sufficient with the presence of inductive noise, and shield insertion is needed to minimize inductive noise. Using a Keff...
Annealing placement by thermodynamic combinatorial optimization
Juan D Vicente, Juan Lanchares, Román Hermida
Placement is key issue of integrated circuit physical design. There exist some techniques inspired in thermodynamics coping with this problem as Simulated Annealing. In this article, we present a combinatorial optimization method directly derived...
An adaptive cryptographic engine for internet protocol security architectures
Andreas Dandalis, Viktor K. Prasanna
Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters....
Frequent value encoding for low power data buses
Jun Yang, Rajiv Gupta, Chuanjun Zhang
Since the I/O pins of a CPU are a significant source of energy consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. Modest reductions in switching can be achieved for data and address buses...