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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10 Issue 2, April 2005

Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques
Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria
Pages: 187-204
DOI: 10.1145/1059876.1059877
Data dependency constraints constitute a lower bound P on the minimal clock period of single-phase clocked sequential circuits. In contrast to methods based on basic retiming, clocked sequential circuits with clock period P can always be obtained...

Synthesis of skewed logic circuits
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
Pages: 205-228
DOI: 10.1145/1059876.1059878
Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the...

Optimizing instruction TLB energy using software and hardware techniques
I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, G. Chen
Pages: 229-257
DOI: 10.1145/1059876.1059879
Power consumption and power density for the Translation Look-aside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. After pointing out the importance of instruction TLB (iTLB) power...

Efficient techniques for transition testing
Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
Pages: 258-278
DOI: 10.1145/1059876.1059880
Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address...

A detailed power model for field-programmable gate arrays
Kara K. W. Poon, Steven J. E. Wilton, Andy Yan
Pages: 279-302
DOI: 10.1145/1059876.1059881
Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This...

Optimized wafer-probe and assembled package test design for analog circuits
Soumendu Bhattacharya, Abhijit Chatterjee
Pages: 303-329
DOI: 10.1145/1059876.1059882
It is well known that wafer-probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much of the testing process into wafer-probe testing as possible to...

Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
Saraju P. Mohanty, N. Ranganathan
Pages: 330-353
DOI: 10.1145/1059876.1059883
Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling...

Voltage scheduling under unpredictabilities: a risk management paradigm
Azadeh Davoodi, Ankur Srivastava
Pages: 354-368
DOI: 10.1145/1059876.1059884
This article addresses the problem of voltage scheduling in unpredictable situations. The voltage scheduling problem assigns voltages to operations such that the power is minimized under a clock delay constraint. In the presence of...

Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
Zhong Wang, Xiaobo Sharon Hu
Pages: 369-388
DOI: 10.1145/1059876.1059885
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures presents a great challenge to compiler design. In this article, we...

Large-scale circuit placement
Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan
Pages: 389-430
DOI: 10.1145/1059876.1059886
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has...