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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10 Issue 3, July 2005

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
Joann M. Paul, Donald E. Thomas, Andrew S. Cassidy
Pages: 431-461
DOI: 10.1145/1080334.1080335
Heterogeneous multiprocessing is the future of chip design with the potential for tens to hundreds of programmable elements on single chips within the next several years. These chips will have heterogeneous, programmable hardware elements that lead...

A framework for systematic validation and debugging of pipeline simulators
Arnab Roy, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti
Pages: 462-491
DOI: 10.1145/1080334.1080336
Microprocessor pipeline simulation at the system level is an extremely important activity in the architecture exploration process. In this article, we address the problem of validating and debugging a pipeline simulator from the specific perspective...

The open family of temporal logics: Annotating temporal operators with input constraints
Ansuman Banerjee, Pallab Dasgupta
Pages: 492-522
DOI: 10.1145/1080334.1080337
Assume-guarantee style verification of modules relies on the appropriate modeling of the interaction of the module with its environment. Popular temporal logics such as Computation Tree Logic (CTL) and Linear Temporal Logic (LTL) that were originally...

Behavioral synthesis techniques for intellectual property protection
Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak
Pages: 523-545
DOI: 10.1145/1080334.1080338
We introduce dynamic watermarking techniques for protecting the value of intellectual property of CAD and compilation tools and reusable design components. The essence of the new approach is the addition of a set of design and timing constraints...

Routing-aware scan chain ordering
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
Pages: 546-560
DOI: 10.1145/1080334.1080339
Scan chain insertion can have a large impact on routability, wirelength, and timing of the design. We present a routing-driven methodology for scan chain ordering with minimum wirelength objective. A routing-based approach to scan chain...

An algorithm for integrated pin assignment and buffer planning
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
Pages: 561-572
DOI: 10.1145/1080334.1080340
The buffer block methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this article, we present a polynomial-time exact...

An o(min(m, n)) parallel deadlock detection algorithm
Jaehwan John Lee, Vincent John Mooney, III
Pages: 573-586
DOI: 10.1145/1080334.1080341
This article presents a novel Parallel Deadlock Detection Algorithm (PDDA) and its hardware implementation, Deadlock Detection Unit (DDU). PDDA uses simple Boolean representations of request, grant, and no activity so that the hardware implementation...