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Design Automation of Electronic Systems (TODAES)

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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10 Issue 4, October 2005

Introduction
Ian G. Harris
Pages: 587-588
DOI: 10.1145/1109118.1109119

XFM: An incremental methodology for developing formal models
Syed M. Suhaib, Deepak A. Mathaikutty, Sandeep K. Shukla, David Berner
Pages: 589-609
DOI: 10.1145/1109118.1109120
We present an agile formal methodology named eXtreme Formal Modeling (XFM), based on Extreme Programming (XP) concepts to construct abstract models from natural language specifications of complex systems. In particular, we focus on Prescriptive...

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
Masahiro Fujita
Pages: 610-626
DOI: 10.1145/1109118.1109121
In this article, we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence...

Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
Tao Feng, Li-C Wang, Kwang-Ting (Tim) Cheng, Chih-Chang (Andy) Lin
Pages: 627-650
DOI: 10.1145/1109118.1109122
In this article, we propose a symbolic simulation method where Boolean functions can be efficiently manipulated through a 2-domain partitioned OBDD data structure. The functional partition is applied by automatically exploring the key decision points...

Simplifying the design and automating the verification of pipelines with structural hazards
Jason T. Higgins, Mark D. Aagaard
Pages: 651-672
DOI: 10.1145/1109118.1109123
This article describes a technique that simplifies the design of pipelined circuits automates the specification and verification of structural-hazard and datapath correctness properties for pipelined circuits. The technique is based upon a template...

Instruction-level test methodology for CPU core self-testing
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabdein Navabi
Pages: 673-689
DOI: 10.1145/1109118.1109124
TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced...

Test chip experimental results on high-level structural test
Ahmad A. Al-Yamani, Edward J. McCluskey
Pages: 690-701
DOI: 10.1145/1109118.1109125
Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes ATPG faster and potentially reduces the size of the test set that needs to be applied. A variety...

An event-based monitoring service for networks on chip
Calin Ciordas, Twan Basten, Andrei Rădulescu, Kees Goossens, Jef Van Meerbergen
Pages: 702-723
DOI: 10.1145/1109118.1109126
Networks on chip (NoCs) are a scalable interconnect solution for multiprocessor systems on chip. We propose a generic reconfigurable online event-based NoC monitoring service, based on hardware probes attached to NoC components, offering run-time...