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Zero cost indexing for improved processor cache performance
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory...
Word-length optimization for differentiable nonlinear systems
George A. Constantinides
This article introduces an automatic design procedure for determining the sensitivity of outputs in a digital signal processing design to small errors introduced by rounding or truncation of internal variables. The proposed approach can be applied to...
Accurate modeling of substrate resistive coupling for floating substrates
Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud
This article focuses on the formulation of the substrate resistive coupling using boundary element methods, specifically for substrates without grounded backplates (floating substrates). An accurate and numerically stable formulation is presented....
Effective techniques for the generalized low-power binding problem
Azadeh Davoodi, Ankur Srivastava
This article proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First, the generalized low power binding problem is formulated as an...
An interactive codesign environment for domain-specific coprocessors
Patrick Schaumont, Doris Ching, Ingrid Verbauwhede
Energy-efficient embedded systems rely on domain-specific coprocessors for dedicated tasks such as baseband processing, video coding, or encryption. We present a language and design environment called GEZEL that can be used for the design,...
Reliable crosstalk-driven interconnect optimization
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While...
Compile-time area estimation for LUT-based FPGAs
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a...
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt, Alex Nicolau
For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit)...
Compilers for leakage power reduction
Yi-Ping You, Chingren Lee, Jenq Kuen Lee
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power...
Loop scheduling with timing and switching-activity minimization for VLIW DSP
Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin H.-M. Sha
In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. This article develops an instruction-level loop-scheduling technique to reduce both execution time and...
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
In low-power design for battery-driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a...
Two-layer bus routing for high-speed printed circuit boards
Muhammet Mustafa Ozdal, Martin D. F. Wong
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that cannot be handled by traditional algorithms. An important design automation problem for high-speed boards today is routing nets within tight minimum...
Improving the energy behavior of block buffering using compiler optimizations
M. Kandemir, J. Ramanujam, U. Sezer
On-chip caches consume a significant fraction of the energy in current microprocessors. As a result, architectural/circuit-level techniques such as block buffering and sub-banking have been proposed and shown to be very effective in reducing the...