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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11 Issue 2, April 2006

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic
M. Ayala-Rincón, C. H. Llanos, R. P. Jacobi, R. W. Hartenstein
Pages: 251-281
DOI: 10.1145/1142155.1142156
Many algebraic operations can be efficiently implemented as pipe networks in arrays of functional units such as systolic arrays that provide a large amount of parallelism. However, the applicability of classical systolic arrays is restricted to...

Reuse analysis of indirectly indexed arrays
Javed Absar, Francky Catthoor
Pages: 282-305
DOI: 10.1145/1142155.1142157
We propose techniques for identifying and exploiting spatial and temporal reuse for indirectly indexed arrays. Indirectly indexed arrays are those arrays which are, typically, accessed inside multilevel loop nests and whose index expression includes...

Handling inverted temperature dependence in static timing analysis
Ali Dasdan, Ivan Hom
Pages: 306-324
DOI: 10.1145/1142155.1142158
In digital circuit design, it is typically assumed that cell delay increases with decreasing voltage and increasing temperature. This assumption is the basis of the cornering approach with cell libraries in static timing analysis (STA). However, this...

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah H. Yang, Vijay Pitchumani
Pages: 325-345
DOI: 10.1145/1142155.1142159
New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the...

Implicit grading of multiple path delay faults
Saravanan Padmanaban, Spyros Tragoudas
Pages: 346-361
DOI: 10.1145/1142155.1142160
The problem of fault grading for multiple path delay faults is introduced and a method of obtain exact coverage is presented. The faults are represented and manipulated as combinational sets using zero-suppressed binary decision diagrams. The...

Optimal simultaneous module and multivoltage assignment for low power
Deming Chen, Jason Cong, Junjuan Xu
Pages: 362-386
DOI: 10.1145/1142155.1142161
Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow...

On the construction of zero-deficiency parallel prefix circuits with minimum depth
Haikun Zhu, Chung-Kuan Cheng, Ronald Graham
Pages: 387-409
DOI: 10.1145/1142155.1142162
A parallel prefix circuit has n inputs x1, x2, …, xn, and computes the n outputs yi=...

Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality
Mahmut Taylan Kandemir
Pages: 410-441
DOI: 10.1145/1142155.1142163
The next generation embedded architectures are expected to accommodate multiple processors on the same chip. While this makes interprocessor communication less costly as compared to traditional high-end parallel machines, it also makes off-chip...

Concurrent testing of digital microfluidics-based biochips
Fei Su, Sule Ozev, Krishnendu Chakrabarty
Pages: 442-464
DOI: 10.1145/1142155.1142164
We present a concurrent testing methodology for detecting catastrophic faults in digital microfluidics-based biochips and investigate the related problems of test planning and resource optimization. We first show that an integer linear programming...

Systematic dynamic memory management design methodology for reduced memory footprint
David Atienza, Jose M. Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor
Pages: 465-489
DOI: 10.1145/1142155.1142165
New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they must heavily rely on Dynamic Memory (DM) due to the unpredictability of the input data (e.g., 3D...

LVS verification across multiple power domains for a quad-core microprocessor
Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou
Pages: 490-500
DOI: 10.1145/1142155.1142166
A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is...

A survey of fault tolerant methodologies for FPGAs
Jason A. Cheatham, John M. Emmert, Stan Baumgart
Pages: 501-533
DOI: 10.1145/1142155.1142167
A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range from simple architectural redundancy to fully on-line adaptive implementations. The applications of these methods also differ; some are used only for manufacturing...