ACM DL

Design Automation of Electronic Systems (TODAES)

Menu

Search Issue
enter search term and/or author name

Archive


DAC '04: Proceedings of the 41st annual Design Automation Conference

Introduction to special issue: Novel paradigms in system-level design
Massoud Pedram
Pages: 535-536
DOI: 10.1145/1142980.1142981

System level design paradigms: Platform-based design and communication synthesis
Alessandro Pinto, Alvise Bonivento, Allberto L. Sangiovanni-Vincentelli, Roberto Passerone, Marco Sgroi
Pages: 537-563
DOI: 10.1145/1142980.1142982
Embedded system level design must be based on paradigms that make formal foundations and unification a cornerstone of their construction. Platform-Based designs and communication synthesis are important components of the paradigm shift we...

Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora
Pages: 564-592
DOI: 10.1145/1142980.1142983
Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex...

Analysis and optimization of distributed real-time embedded systems
Paul Pop, Petru Eles, Zebo Peng, Traian Pop
Pages: 593-625
DOI: 10.1145/1142980.1142984
An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware and software components,...

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
Prabhat Mishra, Aviral Shrivastava, Nikil Dutt
Pages: 626-658
DOI: 10.1145/1142980.1142985
Advances in semiconductor technology permit increasingly complex applications to be realized using programmable systems-on-chips (SOCs). Furthermore, shrinking time-to-market demands, coupled with the need for product versioning through software...

Warp Processors
Roman Lysecky, Greg Stitt, Frank Vahid
Pages: 659-681
DOI: 10.1145/1142980.1142986
We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that...

Module placement for fault-tolerant microfluidics-based biochips
Fei Su, Krishnendu Chakrabarty
Pages: 682-710
DOI: 10.1145/1142980.1142987
Microfluidics-based biochips are soon expected to revolutionize clinical diagnosis, DNA sequencing, and other laboratory procedures involving molecular biology. Most microfluidic biochips today are based on the principle of continuous fluid flow and...

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing
Narender Hanchate, Nagarajan Ranganathan
Pages: 711-739
DOI: 10.1145/1142980.1142988
The continuous scaling of interconnect wires in deep submicron (DSM) circuits results in increased interconnect delay, power, and crosstalk noise. In this work, we develop a game-theoretic framework and multimetric optimization algorithms for the...

Simultaneous placement with clustering and duplication
Gang Chen, Jason Cong
Pages: 740-772
DOI: 10.1145/1142980.1142989
Clustering, duplication, and placement are critical steps in a cluster-based FPGA design flow. Clustering has a great impact on the wirelength, timing, and routability of a circuit. Logic duplication is an effective method for improving performance...

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
Pages: 773-796
DOI: 10.1145/1142980.1142990
We propose a novel, nonsimulative probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to...