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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11 Issue 4, October 2006

Postlayout optimization for synthesis of Domino circuits
Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh
Pages: 797-821
DOI: 10.1145/1179461.1179462
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this article, we propose a synthesis scheme to reduce the duplication cost by...

Synthesis of time-constrained multitasking embedded software
André C. Nácul, Tony Givargis
Pages: 822-847
DOI: 10.1145/1179461.1179463
In modern embedded systems, software development plays a vital role. Many key functions are being migrated to software, aiming at a shorter time to market and easier upgrades. Multitasking is increasingly common in embedded software, and many of...

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters
Kunhyuk Kang, Bipul C. Paul, Kaushik Roy
Pages: 848-879
DOI: 10.1145/1179461.1179464
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this article, we propose a new algorithm for statistical static timing analysis (SSTA) using levelized covariance...

Decomposition of instruction decoders for low-power designs
Wu-An Kuo, Tingting Hwang, Allen C.-H. Wu
Pages: 880-889
DOI: 10.1145/1179461.1179465
During the execution of processor instruction, decoding the instructions is a major task in identifying instructions and generating control signals for data paths. In this article, we propose two instruction decoder decomposition techniques for...

Crosstalk minimization in logic synthesis for PLAs
Yi-Yu Liu, Kuo-Hua Wang, Tingting Hwang
Pages: 890-915
DOI: 10.1145/1179461.1179466
We propose a maximum crosstalk effect minimization algorithm that takes logic synthesis into consideration for PLA structures. To minimize the crosstalk effect, a technique for permuting wire is used which contains the following steps. First, product...

Test sequence generation for controller verification and test with high coverage
Sezer Gören, F. Joel Ferguson
Pages: 916-938
DOI: 10.1145/1179461.1179467
Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test...

Multiple wire reconnections based on implication flow graph
Zhong-Zhen Wu, Shih-Chieh Chang
Pages: 939-952
DOI: 10.1145/1179461.1179468
Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a time by modeling the problem of multiple wire reconnections with a flow graph, and then solving the problem using the maxflow-mincut algorithm on the flow graph....

Performance-driven technology mapping with MSG partition and selective gate duplication
Chi-Shong Wang, Chingwei Yeh
Pages: 953-973
DOI: 10.1145/1179461.1179469
Traditionally, technology mapping is done by first partitioning a circuit into a forest of trees. Each individual tree is then mapped using dynamic programming. The links among the mappings of different trees are provided via propagating the...