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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 Issue 1, January 2007

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures
Anup Gangwar, M. Balakrishnan, Anshul Kumar
Article No.: 1
DOI: 10.1145/1188275.1188276

VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to...

System-level performance/power analysis for platform-based design of multimedia applications
Nicholas H. Zamora, Xiaoping Hu, Radu Marculescu
Article No.: 2
DOI: 10.1145/1188275.1188277

The objective of this article is to introduce the use of Stochastic Automata Networks (SANs) as an effective formalism for application-architecture modeling in system-level average-case analysis for platform-based design. By platform, we mean a...

Area reduction by deadspace utilization on interconnect optimized floorplan
Chiu-Wing Sham, Evangeline F. Y. Young
Article No.: 3
DOI: 10.1145/1188275.1188278

Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the...

Scan-BIST based on cluster analysis and the encoding of repeating sequences
Lei Li, Zhanglei Wang, Krishnendu Chakrabarty
Article No.: 4
DOI: 10.1145/1188275.1188279

We present a built-in self-test (BIST) approach for full-scan designs that extracts the most frequently occurring sequences from deterministic test patterns. The extracted sequences are stored on-chip, and are used during test application. Three...

Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints
Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy
Article No.: 5
DOI: 10.1145/1188275.1188280

This article proposes a new online voltage scaling (VS) technique for battery-powered embedded systems with real-time constraints. The VS technique takes into account the execution times and discharge currents of tasks to further reduce the...

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
Xinping Zhu, Sharad Malik
Article No.: 6
DOI: 10.1145/1188275.1188281

In multiprocessor-based SoCs, optimizing the communication architecture is often as important, if not more important, than optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of...

Hierarchical partitioning of VLSI floorplans by staircases
Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das
Article No.: 7
DOI: 10.1145/1188275.1188282

This article addresses the problem of recursively bipartitioning a given floorplan F using monotone staircases. At each level of the hierarchy, a monotone staircase from one corner of F to its opposite corner is identified, such that...

Instruction set synthesis with efficient instruction encoding for configurable processors
Jong-Eun Lee, Kiyoung Choi, Nikil D. Dutt
Article No.: 9
DOI: 10.1145/1188275.1188283

Application-specific instructions can significantly improve the performance, energy-efficiency, and code size of configurable processors. While generating new instructions from application-specific operation patterns has been a common way to...