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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 Issue 2, April 2007

Editorial
Nikil Dutt
Article No.: 9
DOI: 10.1145/1230800.1230801

Disjunctive image computation for software verification
Chao Wang, Zijiang Yang, Franjo Ivančić, Aarti Gupta
Article No.: 10
DOI: 10.1145/1230800.1230802

Existing BDD-based symbolic algorithms designed for hardware designs do not perform well on software programs. We propose novel techniques based on unique characteristics of software programs. Our algorithm divides an image computation step into a...

Transition-overhead-aware voltage scheduling for fixed-priority real-time systems
Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
Article No.: 11
DOI: 10.1145/1230800.1230803

Time transition overhead is a critical problem for hard real-time systems that employ dynamic voltage scaling (DVS) for power and energy management. While it is a common practice of much previous work to ignore transition overhead, these...

Prediction of leakage power under process uncertainties
Hongliang Chang, Sachin S. Sapatnekar
Article No.: 12
DOI: 10.1145/1230800.1230804

In this article, we present a method to analyze the total leakage current of a circuit under process variations, considering interdie and intradie variations as well as the effect of the spatial correlations of intradie variations. The approach...

A model-based extensible framework for efficient application design using FPGA
Sumit Mohanty, Viktor K. Prasanna
Article No.: 13
DOI: 10.1145/1230800.1230805

For an FPGA designer, several choices are available in terms of target FPGA devices, IP-cores, algorithms, synthesis options, runtime reconfiguration, degrees of parallelism, among others, while implementing a design. Evaluation of design...

A predictive decode filter cache for reducing power consumption in embedded processors
Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau
Article No.: 14
DOI: 10.1145/1230800.1230806

With advances in semiconductor technology, power management has increasingly become a very important design constraint in processor design. In embedded processors, instruction fetch and decode consume more than 40% of processor power. This...

DRDU: A data reuse analysis technique for efficient scratch-pad memory management
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
Article No.: 15
DOI: 10.1145/1230800.1230807

In multimedia and other streaming applications, a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce this energy by making copies of frequently used data in a small local...

Low test application time resource binding for behavioral synthesis
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
Article No.: 16
DOI: 10.1145/1230800.1230808

Recent advances in process technology have led to a rapid increase in the density of integrated circuits (ICs). Increased density and the need to test for new types of defects in nanometer technologies have resulted in a tremendous increase in...

A critical-path-aware partial gating approach for test power reduction
Mohammed Elshoukry, Mohammad Tehranipoor, C. P. Ravikumar
Article No.: 17
DOI: 10.1145/1230800.1230809

Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions propagating from the outputs of scan cells...

Forming N-detection test sets without test generation
Irith Pomeranz, Sudhakar M. Reddy
Article No.: 18
DOI: 10.1145/1230800.1230810

We describe a procedure for forming n-detection test sets for n>1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults...

The exact channel density and compound design for generic universal switch blocks
Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
Article No.: 19
DOI: 10.1145/1230800.1230811

A switch block of k sides W terminals on each side is said to be universal (a (k, W)-USB) if it is routable for every set of 2-pin nets of channel density at most W. The generic optimum universal switch block...