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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 Issue 3, August 2007

Introduction to special issue on demonstrable software systems and hardware platforms
Sung Kyu Lim, Massoud Pedram
Article No.: 20
DOI: 10.1145/1255456.1255457

Efficient simulation of critical synchronous dataflow graphs
Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino
Article No.: 21
DOI: 10.1145/1255456.1255458

System-level modeling, simulation, and synthesis using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems, and the synchronous dataflow (SDF) model of computation is widely...

A framework for heterogeneous specification and design of electronic embedded systems in SystemC
Fernando Herrera, Eugenio Villar
Article No.: 22
DOI: 10.1145/1255456.1255459

This work proposes a methodology which enables heterogeneous specification of complex, electronic systems in SystemC supporting the integration of components under different models of computation (MoCs). This feature is necessary in order to deal...

On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches
Hyung Gyu Lee, Naehyuck Chang, Umit Y. Ogras, Radu Marculescu
Article No.: 23
DOI: 10.1145/1255456.1255460

Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from...

PeaCE: A hardware-software codesign environment for multimedia embedded systems
Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo
Article No.: 24
DOI: 10.1145/1255456.1255461

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW...

Efficient power modeling and software thermal sensing for runtime temperature monitoring
Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
Article No.: 25
DOI: 10.1145/1255456.1255462

The evolution of microprocessors has been hindered by increasing power consumption and heat dissipation on die. An excessive amount of heat creates reliability problems, reduces the lifetime of a processor, and elevates the cost of cooling and...

HW-SW emulation framework for temperature-aware design in MPSoCs
David Atienza, Pablo G. Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose M. Mendias, Roman Hermida
Article No.: 26
DOI: 10.1145/1255456.1255463

New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video) while meeting additional design...

Efficient and scalable compiler-directed energy optimization for realtime applications
Po-Kuan Huang, Soheil Ghiasi
Article No.: 27
DOI: 10.1145/1255456.1255464

With continuing shrinkage of technology feature sizes, the share of leakage in total energy consumption of digital systems continues to grow. Coordinated supply voltage and body bias throttling enables the compiler to better optimize the total...

Circuit-simulated obstacle-aware Steiner routing
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
Article No.: 28
DOI: 10.1145/1255456.1255465

This article develops circuit-simulated routing algorithms. We model the routing graph by an RC network with terminals as inputs, and show that the faster an output reaches its peak, the higher the possibility for the corresponding Hanan or escape...

Probabilistic system-on-a-chip architectures
Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem
Article No.: 29
DOI: 10.1145/1255456.1255466

Parameter variations, noise susceptibility, and increasing energy dissipation of cmos devices have been recognized as major challenges in circuit and microarchitecture design in the nanometer regime. Among these, parameter variations and noise...

A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current
Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, Tingting Hwang
Article No.: 30
DOI: 10.1145/1255456.1255467

Multithreshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when a MTCMOS circuit is designed. If the size of sleep transistor is large enough, the circuit...

A verification system for transient response of analog circuits
Tathagato Rai Dastidar, P. P. Chakrabarti
Article No.: 31
DOI: 10.1145/1255456.1255468

We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for...

Postplacement rewiring by exhaustive search for functional symmetries
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
Article No.: 32
DOI: 10.1145/1255456.1255469

We propose two new algorithms for rewiring: a postplacement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. In the first algorithm, we extract small subcircuits consisting of several...

EWD: A metamodeling driven customizable multi-MoC system modeling framework
Deepak Mathaikutty, Hiren Patel, Sandeep Shukla, Axel Jantsch
Article No.: 33
DOI: 10.1145/1255456.1255470

We present the EWD design environment and methodology, a modeling and simulation framework suited for complex and heterogeneous embedded systems with varying degrees of expressibility and modeling fidelity. This environment promotes the use of...

Binary synthesis
Greg Stitt, Frank Vahid
Article No.: 34
DOI: 10.1145/1255456.1255471

Recent high-level synthesis approaches and C-based hardware description languages attempt to improve the hardware design process by allowing developers to capture desired hardware functionality in a well-known high-level source language. However,...

Speedups in embedded systems with a high-performance coprocessor datapath
Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis
Article No.: 35
DOI: 10.1145/1255456.1255472

This article presents the speedups achieved in a generic single-chip microprocessor system by employing a high-performance datapath. The datapath acts as a coprocessor that accelerates computational-intensive kernel sections thereby increasing the...

Event propagation for accurate circuit delay calculation using SAT
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
Article No.: 36
DOI: 10.1145/1255456.1255473

A SAT-based modeling for event propagation in gate-level digital circuits, which is used for accurate calculation of critical delay in combinational and sequential circuits, is presented in this article. The accuracy of the critical delay...