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Temporal floorplanning using the three-dimensional transitive closure subGraph
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Article No.: 37
Improving logic capacity by time-sharing, dynamically reconfigurable Field Gate Programmable Arrays (FPGAs) are employed to handle designs of high complexity and functionality. In this paper, we use a novel graph-based topological floorplan...
Idle energy minimization by mode sequence optimization
Jinfeng Liu, Pai H. Chou
Article No.: 38
This article presents techniques for reducing idle energy by mode-sequence optimization (MSO) under timing constraints. Our component-level CoMSO algorithm computes energy-optimal mode-transition sequences for different lengths of idle intervals....
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
Article No.: 39
This paper presents a new technique, called Adaptive Stochastic Gradient Voltage-and-Task Scheduling (ASG-VTS), for power optimization of multicore hard realtime systems. ASG-VTS combines stochastic and energy-gradient techniques to...
A practical dynamic single assignment transformation
Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor
Article No.: 40
This paper presents a novel method to construct a dynamic single assignment (DSA) form of array intensive, pointer free C programs. A program in DSA form does not perform any destructive update of scalars and array elements; that is, each element...
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Article No.: 41
Clustering L0 buffers is effective for energy reduction in the instruction memory hierarchy of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. Especially in heterogeneous or...
Techniques for the synthesis of reversible Toffoli networks
D. Maslov, G. W. Dueck, D. M. Miller
Article No.: 42
We present certain new techniques for the synthesis of reversible networks of Toffoli gates, as well as improvements to previous methods. Gate count and technology oriented cost metrics are used. Two new synthesis procedures employing Reed-Muller...
MPSoC memory optimization using program transformation
Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre Paulin
Article No.: 43
Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most...
Functional verification of task partitioning for multiprocessor embedded systems
Dipankar Das, P. P. Chakrabarti, Rajeev Kumar
Article No.: 44
With the advent of multiprocessor embedded platforms, application partitioning and mapping have gained primacy as a design step. The output of this design step is a multithreaded partitioned application where each thread is mapped to a processing...
Clock skew scheduling with race conditions considered
Shih-Hsu Huang, Yow-Tyng Nieh
Article No.: 45
In this article, we provide a fresh viewpoint to the interactions between clock skew scheduling and delay insertion. A race-condition-aware (RCA) clock skew scheduling is proposed to determine the clock skew schedule by taking race conditions...
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization
Gang Wang, Wenrui Gong, Brian Derenzi, Ryan Kastner
Article No.: 46
Design space exploration during high-level synthesis is often conducted through ad hoc probing of the solution space using some scheduling algorithm. This is not only time consuming but also very dependent on designer's experience. We propose a...
Low-Power and testable circuit synthesis using Shannon decomposition
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
Article No.: 47
Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance can result in improved test cost and test confidence. In this article, we analyze the testability in a new style of logic...
ILP and heuristic techniques for system-level design on network processor architectures
Chris Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan
Article No.: 48
Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article...
Optimization of polynomial datapaths using finite ring algebra
Sivaram Gopalakrishnan, Priyank Kalla
Article No.: 49
This article presents an approach to area optimization of arithmetic datapaths at register-transfer level (RTL). The focus is on those designs that perform polynomial computations (add, mult) over finite word-length operands (bit-vectors). We...
Modern embedded multimedia and telecommunications systems need to store and access huge amounts of data. This becomes a critical factor for the overall energy consumption, area, and performance of the systems. Loop transformations are essential to...
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power...