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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13 Issue 4, September 2008

Editorial
Massoud Pedram
Article No.: 55
DOI: 10.1145/1391962.1391963

Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu, Ge Yu
Article No.: 56
DOI: 10.1145/1391962.1391964

Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs...

A high-level clustering algorithm targeting dual Vdd FPGAs
Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal
Article No.: 57
DOI: 10.1145/1391962.1391965

Recent advanced power optimizations deployed in commercial FPGAs, laid out a roadmap towards FPGA devices that can be integrated into ultra low power systems. In this article, we present a high-level design tool to support the process of mapping...

Efficiently scheduling runtime reconfigurations
Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Daniel Mozos, Francky Catthoor
Article No.: 58
DOI: 10.1145/1391962.1391966

Due to the emergence of portable devices that must run complex dynamic applications there is a need for flexible platforms for embedded systems. Runtime reconfigurable hardware can provide this flexibility but the reconfiguration latency can...

System-level throughput analysis for process variation aware multiple voltage-frequency island designs
Siddharth Garg, Diana Marculescu
Article No.: 59
DOI: 10.1145/1391962.1391967

The increasing variability in manufacturing process parameters is expected to lead to significant performance degradation in deep submicron technologies. Multiple Voltage-Frequency Island (VFI) design styles with fine-grained, process-variation...

Access pattern-based code compression for memory-constrained systems
Ozcan Ozturk, Mahmut Kandemir, Guangyu Chen
Article No.: 60
DOI: 10.1145/1391962.1391968

As compared to a large spectrum of performance optimizations, relatively less effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, and reliability. In...

A compiler approach to managing storage and memory bandwidth in configurable architectures
Nastaran Baradaran, Pedro C. Diniz
Article No.: 61
DOI: 10.1145/1391962.1391969

Configurable architectures offer the unique opportunity of realizing hardware designs tailored to the specific data and computational patterns of an application code. Customizing the storage structures is becoming increasingly important in...

Auxiliary state machines + context-triggered properties in verification
Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
Article No.: 62
DOI: 10.1145/1391962.1391970

Formal specifications of interface protocols between a design-under-test and its environment mostly consist of two types of correctness requirements, namely (a) a set of invariants that applies throughout the protocol execution and (b) a set of...

Simulation-based verification using Temporally Attributed Boolean Logic
S. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar
Article No.: 63
DOI: 10.1145/1391962.1391971

We propose a specification logic called Temporally Attributed Boolean (TAB) Logic for Assertion Based Verification, which allows us to: (i) represent assertions succinctly, (ii) incorporate data-orientation and (iii) associate timing to design...

Layout-aware scan chain reorder for launch-off-shift transition test coverage
Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li
Article No.: 64
DOI: 10.1145/1391962.1391972

Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan...

Timing-aware power-optimal ordering of signals
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Article No.: 65
DOI: 10.1145/1391962.1391973

A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally...

Effective decap insertion in area-array SoC floorplan design
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
Article No.: 66
DOI: 10.1145/1391962.1391974

As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common...

Constraint-driven floorplan repair
Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack
Article No.: 67
DOI: 10.1145/1391962.1391975

In this work, we propose a new and efficient approach to the floorplan repair problem, where violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human...

Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules
Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
Article No.: 68
DOI: 10.1145/1391962.1391976

As the circuit densities and transistor counts are increasing, the package routing problem is becoming more and more challenging. In this article, we study an important routing problem encountered in typical high-end MCM designs: routing within...