ACM DL

Design Automation of Electronic Systems (TODAES)

Menu

Search Issue
enter search term and/or author name

Archive


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14 Issue 2, March 2009

Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
K. Avnit, V. D'silva, A. Sowmya, S. Ramesh, S. Parameswaran
Article No.: 19
DOI: 10.1145/1497561.1497562

Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for...

System-level PVT variation-aware power exploration of on-chip communication architectures
Sudeep Pasricha, Young-Hwan Park, Nikil Dutt, Fadi J. Kurdahi
Article No.: 20
DOI: 10.1145/1497561.1497563

With the shift towards deep submicron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage,...

Instrumenting AMS assertion verification on commercial platforms
Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough
Article No.: 21
DOI: 10.1145/1497561.1497564

The industry trend appears to be moving towards designs that integrate large digital circuits with multiple analog/RF (radio frequency) interfaces. In the verification of these large integrated circuits, the number of nets that need to be...

Trade-offs in loop transformations
Martin Palkovic, Francky Catthoor, Henk Corporaal
Article No.: 22
DOI: 10.1145/1497561.1497565

Nowadays, multimedia systems deal with huge amounts of memory accesses and large memory footprints. To alleviate the impact of these accesses and reduce the memory footprint, high-level memory exploration and optimization techniques have been...

A cosimulation methodology for HW/SW validation and performance estimation
Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli
Article No.: 23
DOI: 10.1145/1497561.1497566

Cosimulation strategies allow us to simulate and verify HW/SW embedded systems before the real platform is available. In this field, there is a large variety of approaches that rely on different communication mechanisms to implement an efficient...

Dynamic security domain scaling on embedded symmetric multiprocessors
Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro
Article No.: 24
DOI: 10.1145/1497561.1497567

We propose a method for dynamic security-domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources,...

Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
Meikang Qiu, Edwin H. -M. Sha
Article No.: 25
DOI: 10.1145/1497561.1497568

In high-level synthesis for real-time embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied...

Temperature-aware register reallocation for register file power-density minimization
Xiangrong Zhou, Chenjie Yu, Peter Petrov
Article No.: 26
DOI: 10.1145/1497561.1497569

Increased chip temperature has been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the highest temperature compared to all other hardware components in...

Reducing fault dictionary size for million-gate large circuits
Yu-Ru Hong, Juinn-Dar Huang
Article No.: 27
DOI: 10.1145/1497561.1497570

In general, fault dictionary is prevented from practical applications in fault diagnosis due to its extremely large size. Several previous works are proposed for the fault dictionary size reduction. However, some of them fail to bring down the...

Efficient partial scan cell gating for low-power scan-based testing
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Article No.: 28
DOI: 10.1145/1497561.1497571

Gating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and...

Battery voltage modeling for portable systems
Daler Rakhmatov
Article No.: 29
DOI: 10.1145/1497561.1497572

Limited battery life imposes stringent constraints on the operation of battery-powered portable systems. During battery discharge, the battery voltage decreases, until a certain cutoff value is reached, marking the end of battery life. The amount...

External memory layout vs. schematic
Yokesh Kumar, Prosenjit Gupta
Article No.: 30
DOI: 10.1145/1497561.1497573

The circuit represented by a VLSI layout must be verified by checking it against the schematic circuit as an important part of the functional verification step. This involves two central problems of matching the circuit graphs with each other...

Skew-aware polarity assignment in clock tree
Po-Yuan Chen, Kuan-Hsien Ho, Tingting Hwang
Article No.: 31
DOI: 10.1145/1497561.1497574

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers...

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan
Article No.: 32
DOI: 10.1145/1497561.1497575

In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As high-performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we...

FPGA-based hardware acceleration for Boolean satisfiability
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
Article No.: 33
DOI: 10.1145/1497561.1497576

We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in...