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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14 Issue 3, May 2009

SystemJ compilation using the tandem virtual machine approach
Avinash Malik, Zoran Salcic, Partha S. Roop
Article No.: 34
DOI: 10.1145/1529255.1529256

SystemJ is a language based on the Globally Asynchronous Locally Synchronous (GALS) paradigm. A SystemJ program is a collection of GALS nodes, also called clock domains, and each clock domain is a synchronous program that extends the Java...

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture
Jason Cong, Yiping Fan, Junjuan Xu
Article No.: 35
DOI: 10.1145/1529255.1529257

Behavior synthesis and optimization beyond the register-transfer level require an efficient utilization of the underlying platform features. This article presents a platform-based resource binding approach based on a Distributed Register-File...

Playing the trade-off game: Architecture exploration using Coffeee
Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor
Article No.: 36
DOI: 10.1145/1529255.1529258

Modern mobile devices need to be extremely energy efficient. Due to the growing complexity of these devices, energy-aware design exploration has become increasingly important. Current exploration tools often do not support energy estimation, or...

Scenario-based timing verification of multiprocessor embedded applications
Dipankar Das, P. P. Chakrabarti, Rajeev Kumar
Article No.: 37
DOI: 10.1145/1529255.1529259

This work presents a static timing-analysis method for verification of scenario-based real-time properties, on graphical task-level models of embedded applications. Scenario-based properties specify timing constraints which must be honored for...

Methods for power optimization in SOC-based data flow systems
Philippe Grosse, Yves Durand, Paul Feautrier
Article No.: 38
DOI: 10.1145/1529255.1529260

Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband telecommunication algorithms, stringent timing constraints of 4G wireless telecommunication systems require computing-intensive data-driven...

Word-length selection for power minimization via nonlinear optimization
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
Article No.: 39
DOI: 10.1145/1529255.1529261

This article describes the first method for minimizing the dynamic power consumption of a Digital Signal Processing (DSP) algorithm implemented on reconfigurable hardware via word-length optimization. Fast models for estimating the power...

Generating realistic stimuli for accurate power grid analysis
P. Marques Morgado, Paulo F. Flores, L. Miguel Silveira
Article No.: 40
DOI: 10.1145/1529255.1529262

Power analysis tools are an integral component of any current power sign-off methodology. The performance of a design's power grid affects the timing and functionality of a circuit, directly impacting the overall performance. Ensuring power grid...

Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
Hao Yu, Joanna Ho, Lei He
Article No.: 41
DOI: 10.1145/1529255.1529263

The existing work on via allocation in 3D ICs ignores power/ground vias' ability to simultaneously reduce voltage bounce and remove heat. This article develops the first in-depth study on the allocation of power/ground vias in 3D ICs with...

A memetic approach to the automatic design of high-performance analog integrated circuits
Bo Liu, Francisco V. Fernández, Georges Gielen, R. Castro-López, E. Roca
Article No.: 42
DOI: 10.1145/1529255.1529264

This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local...

Selective shielding technique to eliminate crosstalk transitions
Madhu Mutyam
Article No.: 43
DOI: 10.1145/1529255.1529265

With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent...

Custom topology rotary clock router with tree subnetworks
Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner
Article No.: 44
DOI: 10.1145/1529255.1529266

Increasing demands on computing power have spurred the development of faster, higher-density Integrated Circuits (ICs), compounding power and complexity concerns in design budgets. The clock distribution network is a significant contributor to...

High-performance obstacle-avoiding rectilinear steiner tree construction
Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Szu-Chi Wang
Article No.: 45
DOI: 10.1145/1529255.1529267

Rectilinear Steiner trees are used to route signal nets by global and detail routers in VLSI design for a long time. However, in current IC industry, there are significantly increasing obstacles to be considered, such as large-scale power...

Theories and algorithms on single-detour routing for untangling twisted bus
Tan Yan, Martin D. F. Wong
Article No.: 46
DOI: 10.1145/1529255.1529268

Previous works on PCB bus routing assume matched pin ordering on both sides. But in practice, the pin ordering might be mismatched and the nets become twisted. In this article, we propose a preprocessing step to untangle such twisted nets. We also...