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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15 Issue 1, December 2009

Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel
Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin
Article No.: 1
DOI: 10.1145/1640457.1640458

This article presents a new tool for automatic design of application-specific reconfigurable processor extensions based on UPaK (Abstract Unified Patterns Based Synthesis Kernel for Hardware and Software Systems). We introduce...

Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems
Jingqing Mu, Roman Lysecky
Article No.: 2
DOI: 10.1145/1640457.1640459

Warp processing is a recent computing technology capable of autonomously partitioning the critical kernels within an executing software application to hardware circuits implemented within an on-chip FPGA. While previous performance-driven warp...

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou
Article No.: 3
DOI: 10.1145/1640457.1640460

Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage....

Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates
Jaehyun Kim, Chungki Oh, Youngsoo Shin
Article No.: 4
DOI: 10.1145/1640457.1640461

The current use of multi-Vt to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply...

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
Rajeev R. Rao, Vivek Joshi, David Blaauw, Dennis Sylvester
Article No.: 5
DOI: 10.1145/1640457.1640462

Soft errors in combinational logic circuits are emerging as a significant reliability problem for VLSI designs. Technology scaling trends indicate that the soft error rates (SER) of logic circuits will be dominant factor for future technology...

Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers
Li-Pin Chang, Chun-Da Du
Article No.: 6
DOI: 10.1145/1640457.1640463

Solid-state disks (SSDs) are storage devices that emulate hard drives with flash memory. They have been widely deployed in mobile computers as disk drive replacements. Flash memory is organized in terms of erase blocks. With the current...

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
Irith Pomeranz, Sudhakar M. Reddy
Article No.: 7
DOI: 10.1145/1640457.1640464

In enhanced-scan circuits, a two-pattern test < ti, tj > for a transition fault can be obtained by using a test tj that detects a stuck-at fault, and preceding it by a test...

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts
Bert Geelen, Vissarion Ferentinos, Francky Catthoor, Gauthier Lafruit, Diederik Verkest, Rudy Lauwereins, Thanos Stouraitis
Article No.: 8
DOI: 10.1145/1640457.1640465

Exploitation of spatial locality is essential for memories to increase the access bandwidth and to reduce the access-related latency and energy per word. Spatial locality exploitation of a kernel can be improved by modifying placement of data in...

ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming
Kurt Keutzer, Peng Li, Li Shang, Hai Zhou
Article No.: 9
DOI: 10.1145/1640457.1640466