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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15 Issue 2, February 2010

Fast and accurate processor models for efficient MPSoC design
Gunar Schirner, Andreas Gerstlauer, Rainer Dömer
Article No.: 10
DOI: 10.1145/1698759.1698760

With growing system complexity and ever-increasing software content, the development of embedded software for upcoming MPSoC architectures is a tremendous challenge. Traditional ISS-based validation becomes infeasible due to the large...

Serialized parallel code generation framework for MPSoC
Seongnam Kwon, Soonhoi Ha
Article No.: 11
DOI: 10.1145/1698759.1698761

The models of computations that express concurrency naturally are preferred for initial specification of MPSoC system, since popular programming languages such as C and C++ are designed for sequential execution. In our previous work, we proposed a...

Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques
Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe
Article No.: 12
DOI: 10.1145/1698759.1698762

Hardware synthesis is the process by which system-level, Register Transfer (RT)-level, or behavioral descriptions can be turned into real implementations, in terms of logic gates. Scheduling is one of the most time-consuming steps in the overall...

Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs
Mingxuan Yuan, Zonghua Gu, Xiuqiang He, Xue Liu, Lei Jiang
Article No.: 13
DOI: 10.1145/1698759.1698763

FPGAs are widely used in today's embedded systems design due to their low cost, high performance, and reconfigurability. Partially RunTime-Reconfigurable (PRTR) FPGAs, such as Virtex-2 Pro and Virtex-4 from Xilinx, allow part of the FPGA area to...

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen
Article No.: 14
DOI: 10.1145/1698759.1698764

We present the GroundHog 2009 benchmarking suite that evaluates the power consumption of reconfigurable technology for applications targeting the mobile computing domain. This benchmark suite includes seven designs; one design targets fine-grained...

Thermal analysis of multiprocessor SoC applications by simulation and verification
Dipankar Das, P. P. Chakrabarti, Rajeev Kumar
Article No.: 15
DOI: 10.1145/1698759.1698765

Overheating of computer chips leads to degradation of performance and reliability. Therefore, preventing chips from overheating in spite of increased performance requirements has emerged as a major challenge. Since the cost of cooling has been...

Parameterized architecture-level dynamic thermal models for multicore microprocessors
Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala
Article No.: 16
DOI: 10.1145/1698759.1698766

In this article, we propose a new architecture-level parameterized dynamic thermal behavioral modeling algorithm for emerging thermal-related design and optimization problems for high-performance multicore microprocessor design. We propose a new...

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
Article No.: 17
DOI: 10.1145/1698759.1698767

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS...

Reliability analysis of memories protected with BICS and a per-word parity bit
Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley
Article No.: 18
DOI: 10.1145/1698759.1698768

This article presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for...

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection
Somnath Paul, Hamid Mahmoodi, Swarup Bhunia
Article No.: 19
DOI: 10.1145/1698759.1698769

Maximum operating frequency (Fmax) of a system often needs to be determined at multiple operating points, defined by voltage and temperatures. Such calibration is important for the speed binning process, where the...

Call for papers ACM transactions on design automation of electronic systems (TODAES) special section on low-power electronics and design
Naehyuck Chang, Jörg Henkel
Article No.: 20
DOI: 10.1145/1698759.1698770