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A Special Section on Multicore Parallel CAD: Algorithm Design and Programming
Kurt Keutzer, Peng Li, Li Shang, Hai Zhou
Article No.: 21
Efficient and Deterministic Parallel Placement for FPGAs
Adrian Ludwin, Vaughn Betz
Article No.: 22
We describe a parallel simulated annealing algorithm for FPGA placement. The algorithm proposes and evaluates multiple moves in parallel, and has been incorporated into Altera’s Quartus II CAD system. Across a set of 18 industrial benchmark...
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala
Article No.: 23
In this article, we propose a novel floorplanning algorithm for GPUs. Floorplanning is an inherently sequential algorithm, far from the typical programs suitable for Single-Instruction Multiple-Thread (SIMT)-style concurrency in a GPU. We propose...
GPU-Based Parallelization for Fast Circuit Optimization
Yifang Liu, Jiang Hu
Article No.: 24
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit the GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques...
Multithreaded Simulation for Synchronous Dataflow Graphs
Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya
Article No.: 25
For system simulation, Synchronous DataFlow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and...
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
Xiongfei Liao, Thambipillai Srikanthan
Article No.: 26
UNISIM has been shown to ease the development of simulators for multi-/many-core systems. However, UNISIM cycle-level simulations of large-scale multiprocessor systems could be very time consuming. In this article, we propose a systematic...
This article proposes a new algorithm for parallel synchronous simulation of VHDL designs to be executed on desktop computers. Besides executing VHDL processes in parallel, the algorithm focuses on parallelizing the simulation kernel with special...
Locality-Driven Parallel Static Analysis for Power Delivery Networks
Zhiyu Zeng, Zhuo Feng, Peng Li, Vivek Sarin
Article No.: 28
Large VLSI on-chip Power Delivery Networks (PDNs) are challenging to analyze due to the sheer network complexity. In this article, a novel parallel partitioning-based PDN analysis approach is presented. We use the boundary circuit responses of...
In this article, we developed a massively parallel gate-level logical simulator to address the ever-increasing computing demand for VLSI verification. To the best of the authors’ knowledge, this work is the first one to leverage the power of...
Functional verification of modern digital designs is a crucial, time-consuming task impacting not only the correctness of the final product, but also its time to market. At the heart of most of today’s verification efforts is logic...
Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme
Rajdeep Bondade, Dongsheng Ma
Article No.: 31
Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded...
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
Greg Stitt, Frank Vahid
Article No.: 32
We introduce thread warping, a dynamic optimization technique that customizes multicore architectures to a given application by dynamically synthesizing threads into custom accelerator circuits on FPGAs (Field-Programmable Gate Arrays). Thread...
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models
Antara Ain, Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay, Rajdeep Mukhopadhyay, John Gough
Article No.: 33
Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog...
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
Yue Yu, Shangping Ren, Xiaobo Sharon Hu
Article No.: 34
Real-time systems are systems in which their timing behaviors must satisfy a specified set of timing constraints and they often operate in a real-world environment with scarce resources. As a result, the actual runtime performance of these systems...
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard
Article No.: 35
Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital...