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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world, Volume 17 Issue 3, June 2012

Introduction to special section on verification challenges in the concurrent world
Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta
Article No.: 19
DOI: 10.1145/2209291.2209292

Towards the formal verification of cache coherency at the architectural level
Freek Verbeek, Julien Schmaltz
Article No.: 20
DOI: 10.1145/2209291.2209293

Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model-checking, have been successful at verifying high-level protocols, but, to the best of our knowledge, the verification of cache coherency at the...

A full lifecycle performance verification methodology for multicore systems-on-chip
Jim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang
Article No.: 21
DOI: 10.1145/2209291.2209294

Multicore Systems-on-Chip (MCSoC) are comprised of a rich set of processor cores, specialized hardware accelerators, and I/O interfaces. Functional verification of these complex designs is a critical and demanding task, however, focusing only on...

Deterministic replay for message-passing-based concurrent programs
Mohamed Elwakil, Zijiang Yang
Article No.: 22
DOI: 10.1145/2209291.2209295

The Multicore Communications API (MCAPI) is a new message-passing API that was released by the Multicore Association. MCAPI provides an interface designed for closely distributed embedded systems with multiple cores on a chip and/or chips on a...

Verification and coverage of message passing multicore applications
Etem Deniz, Alper Sen, Jim Holt
Article No.: 23
DOI: 10.1145/2209291.2209296

We describe verification and coverage methods for multicore software that uses message passing libraries for communication. Specifically, we provide techniques to improve reliability of software using the new industry standard MCAPI by the...

Directed test generation for validation of multicore architectures
Xiaoke Qin, Prabhat Mishra
Article No.: 24
DOI: 10.1145/2209291.2209297

Functional validation is widely acknowledged as a major challenge for multicore architectures. Directed tests are promising since a significantly smaller number of directed tests can achieve the same coverage goal compared to constrained-random...

Targeted random test generation for power-aware multicore designs
Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis
Article No.: 25
DOI: 10.1145/2209291.2209298

Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test...

A3MAP: Architecture-aware analytic mapping for networks-on-chip
Wooyoung Jang, David Z. Pan
Article No.: 26
DOI: 10.1145/2209291.2209299

In this article, we propose novel and global Architecture-Aware Analytic MAPping (A3MAP) algorithms applied to Networks-on-Chip (NoCs) not only with homogeneous Processing Elements (PEs) on a regular mesh network as done by most previous...

Postscheduling buffer management trade-offs in streaming software synthesis
Mohammad H. Foroozannejad, Trevor Hodges, Matin Hashemi, Soheil Ghiasi
Article No.: 27
DOI: 10.1145/2209291.2209300

Streaming applications, which are abundant in many disciplines such as multimedia, networking, and signal processing, require efficient processing of a seemingly infinite sequence of input data. In the context of streaming software synthesis from...

An ILP solution to address code generation for embedded applications on digital signal processors
Hassan Salamy, J. Ramanujam
Article No.: 28
DOI: 10.1145/2209291.2209301

Digital Signal Processors (DSPs) are a family of embedded processors designed under tight memory, area, and cost constraints. Many DSPs use irregular addressing modes where base-plus-offset mode is not supported. However, they often have Address...

Divide and conquer high-level synthesis design space exploration
Benjamin Carrion Schafer, Kazutoshi Wakabayashi
Article No.: 29
DOI: 10.1145/2209291.2209302

A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for high-level synthesis based on a divide and conquer method called Divide and Conquer Exploration Algorithm (DC-ExpA) is presented. DC-ExpA parses an untimed...

Formal verification of code motion techniques using data-flow-driven equivalence checking
Chandan Karfa, Chittaranjan Mandal, Dipankar Sarkar
Article No.: 30
DOI: 10.1145/2209291.2209303

A formal verification method for checking correctness of code motion techniques is presented in this article. Finite State Machine with Datapath (FSMD) models have been used to represent the input and the output behaviors of each synthesis step....

Model-driven automation for simulation-based functional verification
Éamonn Linehan, Eamonn O'Toole, Siobhán Clarke
Article No.: 31
DOI: 10.1145/2209291.2209304

Developing testbenches for dynamic functional verification of hardware designs is a software-intensive process that lies on the critical path of electronic system design. The increasing capabilities of electronic components is contributing to the...

Fast poisson solvers for thermal analysis
Haifeng Qian, Sachin S. Sapatnekar, Eren Kursun
Article No.: 32
DOI: 10.1145/2209291.2209305

Accurate and efficient thermal analysis for a VLSI chip is crucial, both for sign-off reliability verification and for design-time circuit optimization. To determine an accurate temperature profile, it is important to simulate a die together with...

High-performance clock mesh optimization
Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis
Article No.: 33
DOI: 10.1145/2209291.2209306

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes...

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs
Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai
Article No.: 34
DOI: 10.1145/2209291.2209307

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient solution for power savings. However, the increasing variability of clock...

A fast heuristic approach for parametric yield enhancement of analog designs
Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai
Article No.: 35
DOI: 10.1145/2209291.2209308

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation...