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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17 Issue 4, October 2012

MCEmu: A Framework for Software Development and Performance Analysis of Multicore Systems
Chia-Heng Tu, Shih-Hao Hung, Tung-Chieh Tsai
Article No.: 36
DOI: 10.1145/2348839.2348840

Developing software for heterogeneous multicore systems is particularly challenging even for experienced developers. While emulators have proven useful to application development, very few heterogeneous multicore emulators have been made available...

Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
Bijan Alizadeh
Article No.: 37
DOI: 10.1145/2348839.2348841

The increased parallelism provided by Out-Of-Order (OOO) and superscalar mechanisms have made the control portion of advanced processors more complicated so that the state-of-the-art formal verification techniques for Register-Transfer-Level (RTL)...

Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay, Scott Little, John Havlicek, Srikanth Chandrasekaran
Article No.: 38
DOI: 10.1145/2348839.2348842

The verification community anticipates the adoption of assertions in the Analog and Mixed-Signal (AMS) domain in the near future. Several questions need to be answered before AMS assertions are brought into practice, such as: (a) How will the...

Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design
Hai Lin, Yunsi Fei
Article No.: 39
DOI: 10.1145/2348839.2348843

Application-Specific Instruction set Processor (ASIP) has become an increasingly popular platform for embedded systems because of its high performance, flexibility, and short turn-around time. The hardware extension in ASIPs can speed-up program...

A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors
Hai Lin, Tiansi Hu, Yunsi Fei
Article No.: 40
DOI: 10.1145/2348839.2348844

Application-Specific Instruction set Processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy efficiency offered by the...

Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
An-Ping Wang, Jiwon Hahn, Mahshid Roumi, Pai H. Chou
Article No.: 41
DOI: 10.1145/2348839.2348845

This article presents a buffer minimization scheme with low dispatching overhead for embedded software processes. To accomplish this, we exploit behavioral transparency in the model of computation. In such a model (e.g., synchronous dataflow), the...

An Algorithm for Jointly Optimizing Quantization and Multiple Constant Multiplication
Matthew B. Gately, Mark B. Yeary, Choon Yik Tang
Article No.: 42
DOI: 10.1145/2348839.2348846

This article presents a joint framework for quantization and Multiple Constant Multiplication (MCM) optimization, which yields a computationally efficient implementation of multiplierless multiplication in hardware and software. Frameworks of this...

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
Yonghwan Kim, Sanghoon Kwak, Taewhan Kim
Article No.: 43
DOI: 10.1145/2348839.2348847

Satisfying the timing constraint is the utmost concern in the integrated circuit design and it is true that most critical timing paths in a circuit cover one or more arithmetic components such as adder, subtractor, and multiplier of which addition...

The Synthesis of Cyclic Dependencies with Boolean Satisfiability
John D. Backes, Marc D. Riedel
Article No.: 44
DOI: 10.1145/2348839.2348848

The accepted wisdom is that combinational circuits must have acyclic (i.e., feed-forward) topologies. Yet simple examples suggest that this is incorrect. In fact, introducing cycles (i.e., feedback) into combinational designs can lead to...

Static NBTI Reduction Using Internal Node Control
David R. Bild, Robert P. Dick, Gregory E. Bok
Article No.: 45
DOI: 10.1145/2348839.2348849

Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units, because these units...

Conditional Diagnosability of k-Ary n-Cubes under the PMC Model
Nai-Wen Chang, Tzu-Yin Lin, Sun-Yuan Hsieh
Article No.: 46
DOI: 10.1145/2348839.2348850

Processor fault diagnosis plays an important role in measuring the reliability of multiprocessor systems and the diagnosis of many well-known interconnection networks. The conditional diagnosability, which is more general than the classical...

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta
Article No.: 47
DOI: 10.1145/2348839.2348851

We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the...

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
Article No.: 48
DOI: 10.1145/2348839.2348852

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous...

Migration-Resistant Policies for Probe-Wear Leveling in MEMS Storage Devices
Mohammed G. Khatib
Article No.: 49
DOI: 10.1145/2348839.2348853

Probes (read/write heads) in a MEMS storage device are susceptible to wear. We study probe wear, and analyze the causes of uneven wear. We show that under real-world workloads some probes can wear one order of magnitude faster than others. This...

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu
Article No.: 50
DOI: 10.1145/2348839.2348854

Rewiring is known to be a class of logic restructuring technique that is at least equally powerful in flexibility compared to other logic transformation techniques. Especially it is wiring sensitive and is particularly useful for...

Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
Ruijing Shen, Sheldon X.-D. Tan, Hai Wang, Jinjun Xiong
Article No.: 51
DOI: 10.1145/2348839.2348855

In this article, we present a new full-chip statistical leakage estimation considering the spatial correlation condition (strong or weak). The new algorithm can deliver linear time, O(N), time complexity, where N is the number...