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Design Automation of Electronic Systems (TODAES)

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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 1 Issue 4, Oct. 1996

Gate-level test generation for sequential circuits
Kwang-Ting Cheng
Pages: 405-442
DOI: 10.1145/238997.238999
This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques for sequential circuits. The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail. The...

A recursive technique for computing lower-bound performance of schedules
M. Langevin, E. Cerny
Pages: 443-455
DOI: 10.1145/238997.239002
We present a fast recursive technique for estimating lower-bound performance of data path schedules. The method relies on the determination of an ASAPUC a(s Soon As Possible Under Constraint) time-step value for each node of the DFG (Data-Flow...

The Unison algorithm: fast evaluation of Boolean expressions
Rok Sosič, Jun Gu, Robert R. Johnson
Pages: 456-477
DOI: 10.1145/238997.239009
We present a Unison algorithm to evaluate arbitrarily complex Boolean expressions. This novel algorithm, based on the total differential of a Boolean function, enables fast evaluation of Boolean expressions in software. Any combination of...

Optimal wiresizing for interconnects with multiple sources
Jason Cong, Lei He
Pages: 478-511
DOI: 10.1145/238997.239018
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading...

Rectilinear Steiner trees on a checkerboard
Joseph L. Ganley, James P. Cohoon
Pages: 512-522
DOI: 10.1145/238997.239033
The rectilinear Steiner tree problem is to find a minimum-length set of horizontal and vertical line segments that interconnect a given set of points in the plane. Here we study the thumbnail rectilinear Steiner tree problem,...