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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems, Volume 18 Issue 1, January 2013

Introduction to the special section on adaptive power management for energy and temperature-aware computing systems
Ayse Kivilcim Coskun, Yung-Hsiang Lu, Qinru Qiu
Article No.: 1
DOI: 10.1145/2390191.2390192

Hierarchical power management for adaptive tightly-coupled processor arrays
Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
Article No.: 2
DOI: 10.1145/2390191.2390193

We present a self-adaptive hierarchical power management technique for massively parallel processor architectures, supporting a new resource-aware parallel computing paradigm called invasive computing. Here, an application can dynamically claim,...

Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
Meeta Srivastav, M. B. Henry, Leyla Nazhandali
Article No.: 3
DOI: 10.1145/2390191.2390194

Voltage scaling has been a prevalent method of saving energy for energy-constrained applications. However, current technology trends which shrink transistors sizes exacerbate process variation effects in voltage-scaled systems. Large variations in...

A self-tuning design methodology for power-efficient multi-core systems
Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman Lysecky, Karthik Shankar, Janet Roveda
Article No.: 4
DOI: 10.1145/2390191.2390195

This article aims to achieve computational reliability and energy efficiency through codevelopment of algorithms, device, and circuit designs for application-specific, reconfigurable architectures. The new methodology characterizes aging-switching...

Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing
Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
Article No.: 5
DOI: 10.1145/2390191.2390196

Asymmetric multi-core processors (AMPs) have been shown to outperform symmetric ones in terms of performance and performance/watt. Improved performance and power efficiency are achieved when the program threads are matched to their most suitable...

Online thermal control methods for multiprocessor systems
Francesco Zanini, David Atienza, Colin N. Jones, Luca Benini, Giovanni De Micheli
Article No.: 6
DOI: 10.1145/2390191.2390197

With technological advances, the number of cores integrated on a chip is increasing. This in turn is leading to thermal constraints and thermal design challenges. Temperature gradients and hotspots not only affect the performance of the system but...

Thermal prediction and adaptive control through workload phase detection
Ryan Cochran, Sherief Reda
Article No.: 7
DOI: 10.1145/2390191.2390198

Elevated die temperature is a true limiter to the scalability of modern processors. With continued technology scaling in order to meet ever-increasing performance demands, it is no longer cost effective to design cooling systems that handle the...

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou
Article No.: 8
DOI: 10.1145/2390191.2390199

NAND flash memory has been employed as disk cache in recent years. It has the advantages of high performance, low leakage power, and cost efficiency. However, flash memory's performance is limited by the inability of in-place updates, coarse...

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan
Article No.: 9
DOI: 10.1145/2390191.2390200

Modern embedded systems need to support multiple time-constrained multimedia applications that often employ multiprocessor-systems-on-chip (MPSoCs). Such systems need to be optimized for resource usage and energy consumption. It is well understood...

Concurrency-aware compiler optimizations for hardware description languages
Kalyan Saladi, Harikumar Somakumar, Mahadevan Ganapathi
Article No.: 10
DOI: 10.1145/2390191.2390201

In this article, we discuss the application of compiler technology for eliminating redundant computation in hardware simulation. We discuss how concurrency in hardware description languages (HDLs) presents opportunities for expression reuse across...

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
Sotirios Xydis, Kiamal Pekmestzi, Dimitrios Soudris, George Economakos
Article No.: 11
DOI: 10.1145/2390191.2390202

Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level...

Verification work reduction methodology in low-power chip implementation
Masanori Kurimoto, Takeshi Yamamoto, Satoshi Nakano, Atsuto Hanami, Hiroyuki Kondo
Article No.: 12
DOI: 10.1145/2390191.2390203

In order to achieve satisfactory verification for complicated low-power demands in green products, we propose a verification work reduction methodology. It consists of three step, namely virtual, direct actual, and actual model simulations....

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
Article No.: 13
DOI: 10.1145/2390191.2390204

Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the...

Using implications to choose tests through suspect fault identification
Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
Article No.: 14
DOI: 10.1145/2390191.2390205

As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are...

Discrete sizing for leakage power optimization in physical design: A comparative study
Santiago Mok, John Lee, Puneet Gupta
Article No.: 15
DOI: 10.1145/2390191.2390206

While sizing has been studied for over three decades, the absence of a common framework with which to compare methods has made progress difficult to measure. In this article, we compare popular sizing techniques in which gates are chosen from a...

ECO cost measurement and incremental gate sizing for late process changes
John Lee, Puneet Gupta
Article No.: 16
DOI: 10.1145/2390191.2390207

Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an engineering change order (ECO) to correct these problems. We present a framework for performing incremental gate sizing for...