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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18 Issue 2, March 2013

A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
Georgios Kornaros, Dionisios Pnevmatikatos
Article No.: 17
DOI: 10.1145/2442087.2442088

Billion transistor systems-on-chip increasingly require dynamic management of their hardware components and careful coordination of the tasks that they carry out. Diverse real-time monitoring functions assist towards this objective through the...

Runtime verification for multicore SoC with high-quality trace data
Rico Backasch, Christian Hochberger, Alexander Weiss, Martin Leucker, Richard Lasslop
Article No.: 18
DOI: 10.1145/2442087.2442089

Multicore System-on-Chip (SoC) implementations of embedded systems are becoming very popular. In these systems it is possible to spread out computations over many cores. On one hand this leads to better energy efficiency if clock frequencies and...

Coverage-directed observability-based validation for embedded software
José C. Costa, José C. Monteiro
Article No.: 19
DOI: 10.1145/2442087.2442090

Motivated by the need for validation methodologies for embedded systems we propose a method for embedded software testing that can be integrated with existing hardware methods. Existing coverage-directed validation methods guarantee the execution...

t/t-Diagnosability of regular graphs under the PMC model
Chun-An Chen, Sun-Yuan Hsieh
Article No.: 20
DOI: 10.1145/2442087.2442091

A system is t/t-diagnosable if, given any collection of test results, the faulty nodes can be isolated to within a set of at most t nodes provided that the number of faulty nodes does not exceed t. Given an N-vertex...

Synthesis of networks of custom processing elements for real-time physical system emulation
Chen Huang, Bailey Miller, Frank Vahid, Tony Givargis
Article No.: 21
DOI: 10.1145/2442087.2442092

Emulating a physical system in real-time or faster has numerous applications in cyber-physical system design and deployment. For example, testing of a cyber-device's software (e.g., a medical ventilator) can be done via interaction with a...

Resource-aware architectures for adaptive particle filter based visual target tracking
Domenic Forte, Ankur Srivastava
Article No.: 22
DOI: 10.1145/2442087.2442093

There are a growing number of visual tracking applications now being envisioned for mobile devices. However, since computer vision algorithms such as particle filtering have large computational demands, they can result in high energy consumption...

Shared recovery for energy efficiency and reliability enhancements in real-time applications with precedence constraints
Baoxian Zhao, Hakan Aydin, Dakai Zhu
Article No.: 23
DOI: 10.1145/2442087.2442094

While Dynamic Voltage Scaling (DVS) remains as a popular energy management technique for modern computing systems, recent research has identified significant and negative impacts of voltage scaling on system reliability. To preserve system...

Achieving autonomous power management using reinforcement learning
Hao Shen, Ying Tan, Jun Lu, Qing Wu, Qinru Qiu
Article No.: 24
DOI: 10.1145/2442087.2442095

System level power management must consider the uncertainty and variability that come from the environment, the application and the hardware. A robust power management technique must be able to learn the optimal decision from past events and...

Reducing instruction bit-width for low-power VLIW architectures
Jongwon Lee, Jonghee M. Youn, Doosan Cho, Yunheung Paek
Article No.: 25
DOI: 10.1145/2442087.2442096

VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary....

Low-power resource binding by postsilicon customization
Mehrdad Majzoobi, Joonho Kong, Farinaz Koushanfar
Article No.: 26
DOI: 10.1145/2442087.2442097

This article proposes the first postsilicon customization method for resource binding to achieve power reduction application specific integrated circuits (ASICs) design. Instead of committing to one configuration of resource binding during...

Low-power anti-aging zero skew clock gating
Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan
Article No.: 27
DOI: 10.1145/2442087.2442098

In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities,...

Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors
Hai Wang, Sheldon X.-D. Tan, Duo Li, Ashish Gupta, Yuan Yuan
Article No.: 28
DOI: 10.1145/2442087.2442099

Efficient temperature estimation is vital for designing thermally efficient, lower power and robust integrated circuits in nanometer regime. Thermal simulation based on the detailed thermal structures no longer meets the demanding tasks for...

IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications
Zhiyu Zeng, Suming Lai, Peng Li
Article No.: 29
DOI: 10.1145/2442087.2442100

Modern IC power delivery systems encompass large on-chip passive power grids and active on-chip or off-chip voltage converters and regulators. While there exists little work targeting on holistic design of such complex IC subsystems, the optimal...

A study of row-based area-array I/O design planning in concurrent chip-package design flow
Ren-Jie Lee, Hung-Ming Chen
Article No.: 30
DOI: 10.1145/2442087.2442101

IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system...

Revisiting automated physical synthesis of high-performance clock networks
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
Article No.: 31
DOI: 10.1145/2442087.2442102

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and...

BonnRoute: Algorithms and data structures for fast and good VLSI routing
Michael Gester, Dirk Müller, Tim Nieberg, Christian Panten, Christian Schulte, Jens Vygen
Article No.: 32
DOI: 10.1145/2442087.2442103

We present the core elements of BonnRoute: advanced data structures and algorithms for fast and high-quality routing in modern technologies. Global routing is based on a combinatorial approximation scheme for min-max resource sharing. Detailed...

The survivability of design-specific spare placement in FPGA architectures with high defect rates
Amit Agarwal, Jason Cong, Brian Tagiku
Article No.: 33
DOI: 10.1145/2442087.2442104

We address the problem of optimizing fault tolerance in FPGA architectures with high defect rates (such as nano-FPGAs) without significantly degrading performance. Our methods address fault tolerance during the placement and reconfiguration stages...