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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18 Issue 3, July 2013

On bottleneck analysis in stochastic stream processing
Raj Rao Nadakuditi, Igor L. Markov
Article No.: 34
DOI: 10.1145/2491477.2491478

Past improvements in clock frequencies have traditionally been obtained through technology scaling, but most recent technology nodes do not offer such benefits. Instead, parallelism has emerged as the key driver of chip-performance growth....

How to efficiently implement dynamic circuit specialization systems
Fatma Abouelella, Tom Davidson, Wim Meeus, Karel Bruneel, Dirk Stroobandt
Article No.: 35
DOI: 10.1145/2491477.2491479

Dynamic circuit specialization (DCS) is a technique used to implement FPGA applications where some of the input data, called parameters, change slowly compared to other inputs. Each time the parameter values change, the FPGA is reconfigured by a...

Thread-based multi-engine model checking for multicore platforms
Gianpiero Cabodi, Sergio Nocco, Stefano Quer
Article No.: 36
DOI: 10.1145/2491477.2491480

This article describes a multithreaded, portfolio-based approach to model checking, where multiple cores are exploited as the underlying computing framework to support concurrent execution of cooperative engines.

We introduce a...

Analysis and minimization of power-transmission loss in locally daisy-chained systems by local energy buffering
Sehwan Kim, Pai H. Chou
Article No.: 37
DOI: 10.1145/2491477.2491481

Power-transmission loss can be a severe problem for low-power embedded systems organized in a daisy-chain topology. The loss can be so high that it can result in failure to power the load in the first place. The first contribution of this article...

Employing circadian rhythms to enhance power and reliability
Saket Gupta, Sachin S. Sapatnekar
Article No.: 38
DOI: 10.1145/2491477.2491482

This article presents a novel scheme for saving architectural power by mitigating delay degradations in digital circuits due to bias temperature instability (BTI), inspired by the notion of human circadian rhythms. The method works in two...

Routability optimization for crossbar-switch structured ASIC design
Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu
Article No.: 39
DOI: 10.1145/2491477.2491483

In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch....

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
Sean Shih-Ying Liu, Wan-Ting Lo, Chieh-Jui Lee, Hung-Ming Chen
Article No.: 40
DOI: 10.1145/2491477.2491484

In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all...

An efficient method for analyzing on-chip thermal reliability considering process variations
Yu-Min Lee, Pei-Yu Huang
Article No.: 41
DOI: 10.1145/2491477.2491485

This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial...

Order statistics for correlated random variables and its application to at-speed testing
Yiyu Shi, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah
Article No.: 42
DOI: 10.1145/2491477.2491486

Although order statistics have been studied for several decades, most of the results are based on the assumption of independent and identically distributed (i.i.d.) random variables. In the literature, how to compute the mth order...

Power-safe application of tdf patterns to flip-chip designs during wafer test
Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty
Article No.: 43
DOI: 10.1145/2491477.2491487

Due to high switching activities in test mode, circuit power consumption is higher than its functional operation. Large switching in the circuit during launch-to-capture cycles not only negatively impacts circuit performance causing overkill, but...

Test compaction for small-delay defects using an effective path selection scheme
Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin
Article No.: 44
DOI: 10.1145/2491477.2491488

Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest testable paths. However, identification of the longest testable paths requires high CPU time, and the sensitization of all such paths leads to large pattern...