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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2 Issue 2, April 1997

Scheduling techniques for variable voltage low power designs
Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu
Pages: 81-97
DOI: 10.1145/253052.253054
This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints...

Functional design for testability of control-dominated architectures
F. Fummi, U. Rovati, D. Sciuto
Pages: 98-122
DOI: 10.1145/253052.253064
Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The...

Parallel logic simulation on a network of workstations using parallel virtual machine
Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson
Pages: 123-134
DOI: 10.1145/253052.253082
This paper explores parallel logic simulation on a network of workstations using a parallel virtual machine (PVM). A novel parallel implementation of the centralized-time event-driven logic simulation algorithm is carried out such that no global...

Hmap: a fast mapper for EPGAs using extended GBDD hash tables
Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen
Pages: 135-150
DOI: 10.1145/253052.253098
A fast and efficient algorithm for technology mapping of electrically programmable gate arrays (EPGAs) is proposed. This Hmap algorithm covers the Boolean network with programmed logic modules bottom-up. The covering operation is based on...

Board-level multiterminal net routing for FPGA-based logic emulation
Wai-Kei Mak, D. F. Wong
Pages: 151-167
DOI: 10.1145/253052.253136
We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [Varghese et al. 1993] and the Enterprise Emulation System [Maliniak 1992] manufactured by Quickturn Design Systems. Optimal...

Analysis of RC interconnections under ramp input
Andrew B. Kahng, Sudhakar Muddu
Pages: 168-192
DOI: 10.1145/253052.253137
We give new methods for calculating the time-domain response for a finite-length distributed RC line that is stimulated by a ramp input. The following are our contributions. First, we obtain the solution of the diffusion...