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CoMETC: Coordinated management of energy/thermal/cooling in servers
Raid Ayoub, Rajib Nath, Tajana Simunic Rosing
Article No.: 1
We introduce a Coordinated Management of Energy, Thermal, and Cooling (CoMETC) technique to minimize cooling and memory energy of server machines. State-of-the-art solutions decouple the optimization of cooling energy costs and energy consumption...
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems
Ra'ed Al-Dujaily, Nizar Dahir, Terrence Mak, Fei Xia, Alex Yakovlev
Article No.: 2
Complex thermal behavior inhibits the advancement of three-dimensional (3D) very-large-scale-integration (VLSI) system designs, as it could lead to ultra-high temperature hotspots and permanent silicon device damage. This article introduces a new...
Improving the performance of port range check for network packet filtering
Yen-Jen Chang, Hsiang-Yu Lu
Article No.: 3
This article introduces a high-performance packet filter design in which we propose the partial parallel range check (PPRC) technique for speeding up port range check. Unlike the conventional serial design that uses cascading cells to perform the...
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes
Angeliki Kritikakou, Francky Catthoor, Vasilios Kelefouras, Costas Goutis
Article No.: 4
Storage-size management techniques aim to reduce the resources required to store elements and to concurrently provide efficient addressing during element accessing. Existing techniques are less appropriate for large iteration spaces with increased...
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yiran Chen, Yinlong Xu, Wei Wang
Article No.: 5
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as...
Performance bound analysis of analog circuits in frequency- and time-domain considering process variations
Xue-Xin Liu, Sheldon X.-D. Tan, Adolfo Adair Palma-Rodriguez, Esteban Tlelo-Cuautle, Guoyong Shi
Article No.: 6
In this article, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chips and manufacture processes. The new method first...
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
Article No.: 7
Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus...
Built-in generation of multicycle functional broadside tests with observation points
Article No.: 8
Functional broadside tests allow overtesting to be avoided as part of a scheme that considers both test generation and the analysis of output responses, by ensuring that delay faults are detected under functional operation conditions. Compared...
Test compaction techniques for assertion-based test generation
Jason G. Tong, Marc Boulé, Zeljko Zilic
Article No.: 9
Assertions are now widely used in verification as a means to help convey designer intent and also to simplify the detection of erroneous conditions by the firing of assertions. With this expressive modeling power, assertions could also be used for...