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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19 Issue 2, March 2014

Performance and power profiling for emulated Android systems
Chia-Heng Tu, Hui-Hsin Hsu, Jen-Hao Chen, Chun-Han Chen, Shih-Hao Hung
Article No.: 10
DOI: 10.1145/2566660

Simulation is a common approach for assisting system design and optimization. For system-wide optimization, energy and computational resources are often the two most critical issues. Monitoring the energy state of each hardware component and...

Performance-driven dynamic thermal management of MPSoC based on task rescheduling
Kunal Ganeshpure, Sandip Kundu
Article No.: 11
DOI: 10.1145/2566661

High level of integration has led to the advent of Multiprocessor System-on-Chip (MPSoC) which consists of multiple processor cores and accelerators on the same die. A MPSoC programming model is based on a task graph where tasks are assigned to...

Cost-effective lifetime and yield optimization for NoC-based MPSoCs
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
Article No.: 12
DOI: 10.1145/2535575

As manufacturing processes scale, designers are increasingly dependent on techniques to mitigate manufacturing defect and permanent failure. In embedded systems-on-chip, system lifetime and yield can be increased using...

Configurable range memory for effective data reuse on programmable accelerators
Jongeun Lee, Seongseok Seo, Jongkyung Paek, Kiyoung Choi
Article No.: 13
DOI: 10.1145/2566662

While programmable accelerators such as application-specific processors and reconfigurable architectures can dramatically speed up compute-intensive kernels of an application, application performance can still be severely limited by...

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network
Eddie Hung, Steven J. E. Wilton
Article No.: 14
DOI: 10.1145/2566668

FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of...

A comparative evaluation of multi-objective exploration algorithms for high-level design
Jacopo Panerati, Giovanni Beltrame
Article No.: 15
DOI: 10.1145/2566669

This article presents a detailed overview and the experimental comparison of 15 multi-objective design-space exploration (DSE) algorithms for high-level design. These algorithms are collected from recent literature and include heuristic,...

Critical-path-aware high-level synthesis with distributed controller for fast timing closure
Seokhyun Lee, Kiyoung Choi
Article No.: 16
DOI: 10.1145/2566670

Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers...

Techniques for scalable and effective routability evaluation
Yaoguang Wei, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy, Andrew D. Huber, Gustavo E. Tellez, Douglas Keller, Sachin S. Sapatnekar
Article No.: 17
DOI: 10.1145/2566663

Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast...

Low-power skewed-load tests based on functional broadside tests
Irith Pomeranz
Article No.: 18
DOI: 10.1145/2566664

This article studies the generation of low-power skewed-load tests such that the signal transitions (and line values) they create during their fast functional clock cycles match those of functional broadside tests. Functional broadside tests...

Design-for-testability for multi-cycle broadside tests by holding of state variables
Irith Pomeranz
Article No.: 19
DOI: 10.1145/2566665

This article describes a design-for-testability approach for increasing the transition fault coverage of multi-cycle broadside tests. Earlier methods addressed two-cycle tests. The importance of multi-cycle tests results from the ability to...

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis
Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton
Article No.: 20
DOI: 10.1145/2566666

Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost. However, many of these...

BLAS: Block-level adaptive striping for solid-state drives
Da-Wei Chang, Hsin-Hung Chen, Dau-Jieu Yang, Hsung-Pin Chang
Article No.: 21
DOI: 10.1145/2555616

Increasing the degree of parallelism and reducing the overhead of garbage collection (GC overhead) are the two keys to enhancing the performance of solid-state drives (SSDs). SSDs employ multichannel architectures, and a data placement scheme in...