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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19 Issue 4, August 2014

Quantifying Notions of Extensibility in FlexRay Schedule Synthesis
Reinhard Schneider, Dip Goswami, Samarjit Chakraborty, Unmesh Bordoloi, Petru Eles, Zebo Peng
Article No.: 32
DOI: 10.1145/2647954

FlexRay has now become a well-established in-vehicle communication bus at most original equipment manufacturers (OEMs) such as BMW, Audi, and GM. Given the increasing cost of verification and the high degree of crosslinking between components in...

Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors
Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai
Article No.: 33
DOI: 10.1145/2629486

Dynamic power management has become an imperative design factor to attain the energy efficiency in modern systems. Among various power management schemes, learning-based policies that are adaptive to different environments and applications have...

WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture
Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul V. Gratz
Article No.: 34
DOI: 10.1145/2647950

WaveSync is a network-on-chip architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components...

Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs
John Jose, Madhu Mutyam
Article No.: 35
DOI: 10.1145/2647952

The efficiency and effectiveness of an adaptive router in an NoC-based multicore system is evaluated by the performance it achieves under varying inter-core communication traffic. A well-designed selection strategy plays an important role in an...

Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing
Kun-Lin Tsai, Hao-Tse Chen, Yo-An Lin
Article No.: 36
DOI: 10.1145/2633604

Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption....

Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation
Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich
Article No.: 37
DOI: 10.1145/2647955

As the technology shrinks, nonfunctional properties (NFPs) such as reliability, vulnerability, power consumption, or heat dissipation become as important as system functionality. As NFPs often influence each other, depend on the application and...

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective
Selvaraj Ravi, M. Joseph
Article No.: 38
DOI: 10.1145/2627754

High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow...

Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors
Da-Cheng Juan, Siddharth Garg, Diana Marculescu
Article No.: 39
DOI: 10.1145/2633606

Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits (ICs). The presence of process variations further exacerbates these problems. In this article, we propose techniques for the...

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation
Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann
Article No.: 40
DOI: 10.1145/2647956

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design...

Understanding SRAM Stability via Bifurcation Analysis: Analytical Models and Scaling Trends
Yenpo Ho, Garng M. Huang, Peng Li
Article No.: 41
DOI: 10.1145/2647957

In the past decades, aggressive scaling of transistor feature size has been a primary force driving higher Static Random Access Memory (SRAM) integration density. Due to technology scaling, nanometer SRAM designs become increasingly vulnerable to...