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Design Automation of Electronic Systems (TODAES)

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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2 Issue 4, Oct. 1997

Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
Min Xu, Fadi J. Kurdahi
Pages: 312-343
DOI: 10.1145/268424.268425
The importance of effective and efficient accounting of layout effects is well established in High-Level Synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics....

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
Michael Münch, Norbert Wehn, Manfred Glesner
Pages: 344-364
DOI: 10.1145/268424.268428
To adopt behavioral synthesis techniques in existing design flows, the synthesis methodology must provide the designer with a mechanism to specify a component's interface timing. This will permit pre- and postsynthesis validation through...

A codesign experiment in acoustic echo cancellation: GMDFα
L. Freund, M. Israel, F. Rousseau, J. M. Bergé, M. Auguin, C. Belleudy, G. Gogniat
Pages: 365-383
DOI: 10.1145/268424.268433
Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Embedded systems have become commonplace in recent years. Since their implementations generally require the use of...

Memory data organization for improved cache performance in embedded processor applications
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Pages: 384-409
DOI: 10.1145/268424.268464
Code generation for embedded processors opens up the possibility for several performance optimization techniques that have been ignored by traditional compilers due to compilation time constraints. We present techniques that take into account...

Code placement techniques for cache miss rate reduction
Hiroyuki Tomiyama, Hiroto Yasuura
Pages: 410-429
DOI: 10.1145/268424.268469
In the design of embedded systems with cache memories, it is important to minimize the cache miss rates to reduce power consumption of the systems as well as improve the performance. In this article, we propose two code placement methods ( a...