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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 20 Issue 1, November 2014

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond
Naehyuck Chang, David Z. Pan, Yuan Xie
Article No.: 1
DOI: 10.1145/2676865

Gate-Level Information Flow Tracking for Security Lattices
Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, Ryan Kastner
Article No.: 2
DOI: 10.1145/2676548

High-assurance systems found in safety-critical infrastructures are facing steadily increasing cyber threats. These critical systems require rigorous guarantees in information flow security to prevent confidential information from leaking to an...

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin
Article No.: 3
DOI: 10.1145/2651401

This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving...

Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL
Lingyi Liu, Shobha Vasudevan
Article No.: 4
DOI: 10.1145/2676549

We enhance STAR, an automatic technique for functional input vector generation for design validation. STAR statically analyzes the source code of the Register-Transfer Level (RTL) design. The STAR approach is a hybrid between RTL symbolic...

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective
Sharad Sinha, Thambipillai Srikanthan
Article No.: 5
DOI: 10.1145/2660769

Area efficiency in datapath synthesis is a widely accepted goal of high-level synthesis. Applications represented by their dataflow graphs are synthesized using resource sharing principles to reduce the area. However, existing resource sharing...

Synthesizing Optimal Switching Lattices
Graeme Gange, Harald Søndergaard, Peter J. Stuckey
Article No.: 6
DOI: 10.1145/2661632

The use of nanoscale technologies to create electronic devices has revived interest in the use of regular structures for defining complex logic functions. One such structure is the switching lattice, a two-dimensional lattice of four-terminal...

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
An-Che Cheng, Chia-Chih (Jack) Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou
Article No.: 7
DOI: 10.1145/2651400

SystemVerilog provides powerful language constructs for verification, and one of them is the covergroup functional coverage model. This model is designed as a complement to assertion verification, that is, it has the advantage of defining...

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor
Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li
Article No.: 8
DOI: 10.1145/2651402

Power efficiency is increasingly critical to battery-powered smartphones. Given that the using experience is most valued by the user, we propose that the power optimization should directly respect the user experience. We conduct a statistical...

Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs
Wen-Li Shih, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee
Article No.: 9
DOI: 10.1145/2668119

Multithread programming is widely adopted in novel embedded system applications due to its high performance and flexibility. This article addresses compiler optimization for reducing the power consumption of multithread programs. A traditional...

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation
Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero
Article No.: 10
DOI: 10.1145/2658988

Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high...

Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression
Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim
Article No.: 11
DOI: 10.1145/2658989

The last few years have witnessed the emergence of a promising new memory technology, namely Phase-Change Memory (PCM). Due to its inherent ability to scale deeply into the nanoscale regime and its low power consumption, PCM is increasingly viewed...

Reducing Contention in Shared Last-Level Cache for Throughput Processors
Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou
Article No.: 12
DOI: 10.1145/2676550

Deploying the Shared Last-Level Cache (SLLC) is an effective way to alleviate the memory bottleneck in modern throughput processors, such as GPGPUs. A commonly used scheduling policy of throughput processors is to render the maximum possible...

A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design
Roopak Sinha, Alain Girault, Gregor Goessler, Partha S. Roop
Article No.: 13
DOI: 10.1145/2663344

A system-on-chip (SoC) contains numerous intellectual property blocks, or IPs. Protocol mismatches between IPs may affect the system-level functionality of the SoC. Mismatches are addressed by introducing converters to control inter-IP...

Multiplierless Design of Folded DSP Blocks
Levent Aksoy, Paulo Flores, Jose Monteiro
Article No.: 14
DOI: 10.1145/2663343

This article addresses the problem of minimizing the implementation cost of the time-multiplexed constant multiplication (TMCM) operation that realizes the multiplication of an input variable by a single constant selected from a set of multiple...

An Efficient Hardware-Based Higher Radix Floating Point MAC Design
Mohamed Asan Basiri M, Noor Mahammad Sk
Article No.: 15
DOI: 10.1145/2667224

This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance...

Design of Hardened Embedded Systems on Multi-FPGA Platforms
Cristiana Bolchini, Chiara Sandionigi
Article No.: 16
DOI: 10.1145/2676551

The aim of this article is the definition of a reliability-aware methodology for the design of embedded systems on multi-FPGA platforms. The designed system must be able to detect the occurrence of faults globally and autonomously, in order to...