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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 20 Issue 3, June 2015

Design of Ultra-Low Power Scalable-Throughput Many-Core DSP Applications
Meeta Srivastav, Mohammed Ehteshamuddin, Kyle Stegner, Leyla Nazhandali
Article No.: 34
DOI: 10.1145/2720018

We propose a system-level solution in designing process variation aware (PVA) scalable-throughput many-core systems for energy constrained applications. In our proposed methodology, we leverage the benefits of voltage scaling for obtaining energy...

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch
Article No.: 35
DOI: 10.1145/2733374

Real-time applications such as multimedia and gaming require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. For FIFO multiplexed on-chip packet switched networks we consider worst-case...

A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications
Nicola Bombieri, Franco Fummi, Sara Vinco
Article No.: 36
DOI: 10.1145/2720019

With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW...

High-Throughput Logic Timing Simulation on GPGPUs
Stefan Holst, Michael E. Imhof, Hans-Joachim Wunderlich
Article No.: 37
DOI: 10.1145/2714564

Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations...

Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating
Tong Xu, Peng Li, Savithri Sundareswaran
Article No.: 38
DOI: 10.1145/2700825

Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the...

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection
Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi B. Tahoori
Article No.: 39
DOI: 10.1145/2746237

Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and...

Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times
Heejong Park, Avinash Malik, Zoran Salcic
Article No.: 40
DOI: 10.1145/2740961

Safety-critical software systems need to guarantee functional correctness and bounded response times to external input events. Programs designed using reactive programming languages, based on formal mathematical semantics, can be automatically...

Explaining Software Failures by Cascade Fault Localization
Qiuping Yi, Zijiang Yang, Jian Liu, Chen Zhao, Chao Wang
Article No.: 41
DOI: 10.1145/2738038

During software debugging, a significant amount of effort is required for programmers to identify the root cause of a manifested failure. In this article, we propose a cascade fault localization method to help speed up this labor-intensive process...

System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems
Jong Chul Lee, Roman Lysecky
Article No.: 42
DOI: 10.1145/2717310

As the complexity of embedded systems rapidly increases, the use of traditional analysis and debug methods encounters significant challenges in monitoring, analyzing, and debugging the complex interactions of various software and hardware...

Lazy-RTGC: A Real-Time Lazy Garbage Collection Mechanism with Jointly Optimizing Average and Worst Performance for NAND Flash Memory Storage Systems
Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Zili Shao
Article No.: 43
DOI: 10.1145/2746236

Due to many attractive and unique properties, NAND flash memory has been widely adopted in mission-critical hard real-time systems and some soft real-time systems. However, the nondeterministic garbage collection operation in NAND flash memory...

Array Interleaving—An Energy-Efficient Data Layout Transformation
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa
Article No.: 44
DOI: 10.1145/2747875

Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. These techniques need to evolve with modern architectures supporting wide memory...

Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips
Sudip Roy, Partha P. Chakrabarti, Srijan Kumar, Krishnendu Chakrabarty, Bhargab B. Bhattacharya
Article No.: 45
DOI: 10.1145/2714562

The recent proliferation of digital microfluidic (DMF) biochips has enabled rapid on-chip implementation of many biochemical laboratory assays or protocols. Sample preprocessing, which includes dilution and mixing of reagents, plays an important...

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation
Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu
Article No.: 46
DOI: 10.1145/2732408

Globalization of the integrated circuit design and manufacturing flow has successfully ameliorated design complexity and fabrication cost challenges, and helped deliver cost-effective products while meeting stringent time-to-market requirements....