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In this article, we propose an efficient finite-element-based (FE-based) method for both steady and transient thermal analyses of high-performance integrated circuits based on the hierarchical matrix (H-matrix) representation....
TCONMAP: Technology Mapping for Parameterised FPGA Configurations
Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt
Article No.: 48
Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular...
Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories
Steffen Peter, Tony Givargis
Article No.: 49
Constraint programming solvers, such as Satisfiability Modulo Theory (SMT) solvers, are capable tools in finding preferable configurations for embedded systems from large design spaces. However, constructing SMT constraint programs is not trivial,...
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding
Ali Mirtar, Sujit Dey, Anand Raghunathan
Article No.: 50
Due to limitations of cooling methods such as using fan and heat sink, dynamic thermal management (DTM) is being widely adopted to manage the temperature of computing systems. However, application of DTM can reduce the system performance and...
VSSD: Performance Isolation in a Solid-State Drive
Da-Wei Chang, Hsin-Hung Chen, Wei-Jian Su
Article No.: 51
Performance isolation is critical in shared storage systems, a popular storage solution. In a shared storage system, interference between requests from different users can affect the accuracy of I/O cost accounting, resulting in poor performance...
An enterprise service-level performance time series is a sequence of data points that quantify demand, throughput, average order-delivery time, quality of service, or end-to-end cost. Analytical and predictive models of such time series can be...
Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines
Ingoo Heo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent Byunghoon Kang, Yunheung Paek
Article No.: 53
In recent years, dynamic program analysis (DPA) has been widely used in various fields such as profiling, finding bugs, and security. However, existing solutions have their own weaknesses. Software solutions provide flexibility in DPA but they...
Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology
Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang
Article No.: 54
Modern mobile processors integrating an increasing number of cores into one single chip demand large-capacity, on-chip, last-level caches (LLCs) in order to achieve scalable performance improvements. However, adopting traditional memory...
Architecting the Last-Level Cache for GPUs using STT-RAM Technology
Mohammad Hossein Samavatian, Mohammad Arjomand, Ramin Bashizade, Hamid Sarbazi-Azad
Article No.: 55
Future GPUs should have larger L2 caches based on the current trends in VLSI technology and GPU architectures toward increase of processing core count. Larger L2 caches inevitably have proportionally larger power consumption. In this article,...
Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration
Leandro Soares Indrusiak, James Harbin, Osmar Marchi Dos Santos
Article No.: 56
An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is...
FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences
Article No.: 57
This article introduces a new approach to extreme static test compaction for functional test sequences that modifies the sequence in order to enhance the ability to omit test vectors from it and thus compact it. In the new approach, modification...
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
Article No.: 58
Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient...
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
R. Iris Bahar, Alex K. Jones, Yuan Xie
Article No.: 59
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods
Bradley T. Kiddie, William H. Robinson, Daniel B. Limbrick
Article No.: 60
As fabrication technology scales towards smaller transistor sizes and lower critical charge, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs), and...
In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors
Leila Delshadtehrani, Hamed Farbeh, Seyed Ghassem Miremadi
Article No.: 61
Scratchpad memories (SPMs) are widely employed in multicore embedded processors. Reliability is one of the major constraints in the embedded processor design, which is threatened with the increasing susceptibility of memory cells to multiple-bit...
Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization
Nikolaos Papandreou, Thomas Parnell, Haralampos Pozidis, Thomas Mittelholzer, Evangelos Eleftheriou, Charles Camp, Thomas Griffin, Gary Tressler, Andrew Walls
Article No.: 62
NAND flash memory is not only the ubiquitous storage medium in consumer applications but has also started to appear in enterprise storage systems as well. MLC and TLC flash technology made it possible to store multiple bits in the same silicon...
Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent...
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism
Renyuan Zhang, Mineo Kaneko
Article No.: 64
The feasibility of designing digitally programmable delay elements (PDEs) employing neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate of the MOS transistor, the current flowing through the transistor can be...
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors
Hyungjun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, Maria K. Michael
Article No.: 65
Moore's Law scaling continues to yield higher transistor density with each succeeding process generation, leading to today's many-core chip multiprocessors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep...
An Improved Methodology for Resilient Design Implementation
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, Jose Pineda De Gyvez
Article No.: 66
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16% and 14% energy penalties due...