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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21 Issue 1, November 2015

FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits
Debashri Roy, Prasun Ghosal, Saraju Mohanty
Article No.: 1
DOI: 10.1145/2767127

The high density of interconnects, closer proximity of modules, and routing phase are pivotal during the layout of a performance-centric three-dimensional integrated circuit (3D IC). Heuristic-based approaches are typically used to handle...

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography
Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
Article No.: 2
DOI: 10.1145/2764904

In this article we present a pairwise coloring (PWC) approach to tackle the layout decomposition problem for triple patterning lithography (TPL). The main idea is to reduce the problem to a set of bi-coloring problems. The overall...

DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors
Hu Chen, Sanghamitra Roy, Koushik Chakraborty
Article No.: 3
DOI: 10.1145/2755558

In this article, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real-world applications. To effectively exploit these delay...

Memory Management Scheme to Improve Utilization Efficiency and Provide Fast Contiguous Allocation without a Statically Reserved Area
Myungsun Kim, Jinkyu Koo, Hyojung Lee, James R. Geraci
Article No.: 4
DOI: 10.1145/2770871

Fast allocation of large blocks of physically contiguous memory plays a crucial role to boost the performance of multimedia applications in modern memory-constrained portable devices, such as smartphones, tablets, etc. Existing systems have...

Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design
Fabian Oboril, Mehdi B. Tahoori
Article No.: 5
DOI: 10.1145/2783435

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to bias temperature instability and hot carrier injection. As a result, device delays increase over time, reducing the mean time to failure (MTTF)...

Locality-Aware Network Utilization Balancing in NoCs
Ankit More, Baris Taskin
Article No.: 6
DOI: 10.1145/2743012

Hierarchical and multi-network networks-on-chip (NoCs) have been proposed in the literature to improve the energy- and performance-efficient scalability of the traditional flat-mesh NoC architecture. Theoretically, based on a small-world...

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference
Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie
Article No.: 7
DOI: 10.1145/2753757

Main memory latencies have become a major performance bottleneck for chip-multiprocessors (CMPs). Since reads are on the critical path, existing memory controllers prioritize reads over writes. However, writes must be eventually processed when the...

An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
Gilberto Ochoa-Ruiz, Sébastien Guillet, Florent De Lamotte, Eric Rutten, El-Bay Bourennane, Jean-Philippe Diguet, Guy Gogniat
Article No.: 8
DOI: 10.1145/2800784

This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This...

Clock Period Minimization with Minimum Leakage Power
Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh
Article No.: 9
DOI: 10.1145/2778954

In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power...

A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching
Anupama R. Subramaniam, Janet Roveda, Yu Cao
Article No.: 10
DOI: 10.1145/2778970

Timing characterization of standard cells is one of the essential steps in VLSI design. The traditional static timing analysis (STA) tool assumes single input switching models for the characterization of multiple input gates. However, due to...

Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy
Dongha Jung, Hokyoon Lee, Seon Wook Kim
Article No.: 11
DOI: 10.1145/2795229

Voltage scaling is known to be an efficient way of saving power and energy within a system, and large caches such as LLCs are good candidates for voltage scaling considering their constantly increasing size. However, the VCCMIN...

Complementary Synthesis for Encoder with Flow Control Mechanism
Ying Qin, Shengyu Shen, Qingbo Wu, Huadong Dai, Yan Jia
Article No.: 12
DOI: 10.1145/2794079

Complementary synthesis automatically generates an encoder's decoder with the assumption that the encoder's all input variables can always be uniquely determined by its output symbol sequence. However, to prevent the faster encoder from...

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation
Irith Pomeranz
Article No.: 13
DOI: 10.1145/2778953

Multicycle tests support test compaction by allowing each test to detect more target faults. The ability of multicycle broadside tests to provide test compaction depends on the ability of primary input sequences to take the circuit between pairs...

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing
Seetal Potluri, A. Satya Trinadh, Sobhan Babu Ch., V. Kamakoti, Nitin Chandrachoodan
Article No.: 14
DOI: 10.1145/2790297

Scan-based testing is crucial to ensuring correct functioning of chips. In this scheme, the scan and capture phases are interleaved. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to...

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
Article No.: 15
DOI: 10.1145/2770872

The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result...

A New Uncertainty Budgeting-Based Method for Robust Analog/Mixed-Signal Design
Jin Sun, Claudio Talarico, Priyank Gupta, Janet Roveda
Article No.: 16
DOI: 10.1145/2778959

This article proposes a novel methodology for robust analog/mixed-signal IC design by introducing a notion of budget of uncertainty. This method employs a new conic uncertainty model to capture process variability and describes...

Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips
Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya
Article No.: 17
DOI: 10.1145/2798726

A digital microfluidic biochip (DMB) is often deployed for multiplexing several assays in space and in time. The residue left by one assay may contaminate the droplets used for subsequent assays. Biochemical assays involving cell culture and those...

Security-Aware Design Methodology and Optimization for Automotive Systems
Chung-Wei Lin, Bowen Zheng, Qi Zhu, Alberto Sangiovanni-Vincentelli
Article No.: 18
DOI: 10.1145/2803174

In this article, we address both security and safety requirements and solve security-aware design problems for the controller area network (CAN) protocol and time division multiple access (TDMA)-based protocols. To provide insights and guidelines...