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A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications
Daming Zhang, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang
Article No.: 19
Developing circuits for streaming applications written in C (or its variants) can benefit greatly from C-to-RTL (C2RTL) synthesis. Yet, most existing C2RTL tools lack system-level options to trade off various design constraints, such as delay and...
Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements
Article No.: 20
Assertion-based verification (ABV) for IP blocks given as synchronous RTL (register transfer level) descriptions has now widely gained acceptance. The challenge addressed here is ABV for systems on chip (SoC) modeled at the system level in...
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs
Article No.: 21
Due to the inappropriate assignment of bump pads or the improper assignment of I/O buffers, the constructed buffered I/O signals in an area-I/O flip-chip design may yield longer maximum delay. In this article, the problem of assigning...
Array Size Computation under Uniform Overlapping and Irregular Accesses
Angeliki Kritikakou, Francky Catthoor, Vasilios Kelefouras, Costas Goutis
Article No.: 22
The size required to store an array is crucial for an embedded system, as it affects the memory size, the energy per memory access, and the overall system cost. Existing techniques for finding the minimum number of resources required to store an...
Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
Youngsik Kim, Sungjoo Yoo, Sunggu Lee
Article No.: 23
Multi-level cell (MLC) phase change RAM (PRAM) is expected to offer lower cost main memory than DRAM. However, poor write performance is one of the most critical problems for practical applications of MLC PRAM. In this article, we present two...
A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing
Dong Xiang, Kele Shen
Article No.: 24
3D technology for networks-on-chip (NOCs) becomes attractive. It is important to present an effective scheme for 3D stacked NOC router and interconnect testing. A new approach to testing of NOC routers is proposed by classifying the routers....
Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction
Zipeng Li, Tsung-Yi Ho, Krishnendu Chakrabarty
Article No.: 25
A digital microfluidic biochip (DMFB) is an attractive technology platform for revolutionizing immunoassays, clinical diagnostics, drug discovery, DNA sequencing, and other laboratory procedures in biochemistry. In most of these applications,...
Parallel Power Grid Analysis Based on Enlarged Partitions
Le Zhang, Vivek Sarin
Article No.: 26
As the size and complexity of current VLSI circuits grows, faster power grid simulation is becoming more and more desirable. In this article, we present a parallel iterative method for static VLSI power grid simulation. In the proposed...
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands
Song Jin, Songwei Pei, Yinhe Han, Huawei Li
Article No.: 27
Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multicore chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or...
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions
Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram
Article No.: 28
In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and...
As technology scales, thermal management for multicore architectures becomes a critical challenge due to increasing power density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the...
Reliability-Aware Resource Allocation and Binding in High-Level Synthesis
Liang Chen, Mojtaba Ebrahimi, Mehdi B. Tahoori
Article No.: 30
Soft error is nowadays a major reliability issue for nanoscale VLSI, and addressing it during high-level synthesis is essential to improve the efficiency of error mitigation. Motivated by the observation that for behavioral designs, especially...
ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes
Jeremy Dubeuf, David Hely, Vincent Beroulle
Article No.: 31
Elliptic Curves Cryptography (ECC) tends to replace RSA for public key cryptographic services. ECC is involved in many secure schemes such as Elliptic Curve Diffie-Hellman (ECDH) key agreement, Elliptic Curve Integrated Encryption Scheme (ECIES),...
Security-Aware Obfuscated Priority Assignment for Automotive CAN Platforms
Martin Lukasiewycz, Philipp Mundhenk, Sebastian Steinhorst
Article No.: 32
Security in automotive in-vehicle networks is an increasing problem with the growing connectedness of road vehicles. This article proposes a security-aware priority assignment for automotive controller area network (CAN) platforms with the aim of...
Adapting to Varying Distribution of Unknown Response Bits
Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev
Article No.: 33
Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices until each device under test either fails or passes each test. With increasing process variations, the statistical...
Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory
Jingweijia Tan, Zhi Li, Mingsong Chen, Xin Fu
Article No.: 34
The increasing adoption of graphics processing units (GPUs) for high-performance computing raises the reliability challenge, which is generally ignored in traditional GPUs. GPUs usually support thousands of parallel threads and require a sizable...
Design-for-Testability for Functional Broadside Tests under Primary Input Constraints
Article No.: 35
Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. When a circuit is embedded in a larger design, a functional broadside test needs to...