Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers, Volume 21 Issue 3, July 2016

Section: Special Section on New Physical Design Techniques for the Next Generation Integration Technology

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology
Evangeline Young, Azadeh Davoodi
Article No.: 36
DOI: 10.1145/2902365

Eh?Placer: A High-Performance Modern Technology-Driven Placer
Nima Karimpour Darav, Andrew Kennings, Aysa Fakheri Tabrizi, David Westwick, Laleh Behjat
Article No.: 37
DOI: 10.1145/2899381

The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent...

Clock-Tree-Aware Incremental Timing-Driven Placement
Vinicius Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz C. V. Dos Santos
Article No.: 38
DOI: 10.1145/2858793

The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step toward timing closure. Current TDP techniques improve critical paths but overlook the impact of register placement on clock...

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching
Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho
Article No.: 39
DOI: 10.1145/2856031

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from...

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect
Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin
Article No.: 40
DOI: 10.1145/2890499

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on-chip communication becomes more and more...

Analytical Clustering Score with Application to Postplacement Register Clustering
Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, Iris Hui-Ru Jiang
Article No.: 41
DOI: 10.1145/2894753

Circuit clustering is usually done through discrete optimizations to enable circuit size reduction or design-specific cluster formation. In this article, we are interested in the register-clustering technique for clock-power reduction by...

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning
Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan
Article No.: 42
DOI: 10.1145/2842612

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, for example, in 14nm and below, for which double-patterning lithography has to be used for manufacturing lower metal routing layers with...

EBL Overlapping Aware Stencil Planning for MCC System
Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan
Article No.: 43
DOI: 10.1145/2888394

Electron beam lithography (EBL) is a promising, maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters)...

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC
Seungwon Kim, Seokhyeong Kang, Ki Jin Han, Youngmin Kim
Article No.: 44
DOI: 10.1145/2894752

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been widely used to reduce the standby leakage energy. In this work, we investigate a power-gating...

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout
Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
Article No.: 45
DOI: 10.1145/2888395

In the MOS analog layout, variability suppression is becoming a major issue, as is layout efficiency. Introducing a transistor array (TA) style to analog layout, this article addresses the layout-dependent variability based on the measurement...

Section: Special Section on New Physical Design Techniques for the Next Generation Integration Technology

Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling
Chao Wang, Chuansheng Dong, Haibo Zeng, Zonghua Gu
Article No.: 46
DOI: 10.1145/2846096

Multicore processors are increasingly adopted in resource-constrained real-time embedded applications. In the development of such applications, efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption...

Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study
Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, Sunggu Lee
Article No.: 47
DOI: 10.1145/2842613

Phase-change memory (PCM) has several benefits including low cost, non-volatility, byte-addressability, etc., and limitations such as write endurance. There have been several hardware approaches to exploit the benefits while minimizing the...

FH-OAOS: A Fast Four-Step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction
Xing Huang, Wenzhong Guo, Genggeng Liu, Guolong Chen
Article No.: 48
DOI: 10.1145/2856033

With the sharp increase of very large-scale integrated (VLSI) circuit density, we are faced with many knotty issues. Particularly in the routing phase of VLSI physical design, the interconnection effects directly relate to the final performance of...

A Survey of Techniques for Cache Locking
Sparsh Mittal
Article No.: 49
DOI: 10.1145/2858792

Cache memory, although important for boosting application performance, is also a source of execution time variability, and this makes its use difficult in systems requiring worst-case execution time (WCET) guarantees. Cache locking is a promising...

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp
Ramachandran Venkatasubramanian, Robert Elio, Sule Ozev
Article No.: 50
DOI: 10.1145/2851490

RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology-node-independent design methodology for these rail clamp circuits that takes process, voltage,...

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
Sangmin Kim, Seokhyeong Kang, Youngsoo Shin
Article No.: 51
DOI: 10.1145/2856032

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock...

Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling
Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu
Article No.: 52
DOI: 10.1145/2870633

In this survey, we review several approaches for predicting performance of Network-on-Chip (NoC)-based multicore systems, starting from the traffic models to the complex NoC models for latency evaluation. We first review typical traffic models to...

Path Selection for Real-Time Communication on Priority-Aware NoCs
Hany Kashif, Hiren Patel, Sebastian Fischmeister
Article No.: 53
DOI: 10.1145/2866572

This work investigates selecting paths for communication flows when deploying a hard real-time application on a chip-multiprocessor system. This chip-multiprocessor system uses a priority-aware real-time network-on-chip interconnect between the...

An Effective Chemical Mechanical Polishing Fill Insertion Approach
Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young
Article No.: 54
DOI: 10.1145/2886097

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying...