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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21 Issue 4, September 2016

Streaming Sorting Networks
Marcela Zuluaga, Peter Milder, Markus Püschel
Article No.: 55
DOI: 10.1145/2854150

Sorting is a fundamental problem in computer science and has been studied extensively. Thus, a large variety of sorting methods exist for both software and hardware implementations. For the latter, there is a trade-off between the throughput...

Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection
Yue Zhao, Taeyoung Kim, Hosoon Shin, Sheldon X.-D. Tan, Xin Li, Haibao Chen, Hai Wang
Article No.: 56
DOI: 10.1145/2875422

Accurately estimating the failure region of rare events for memory-cell and analog circuit blocks under process variations is a challenging task. In this article, we propose a new statistical method, called EliteScope, to estimate the...

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression
Rickard Ewetz, Cheng-Kok Koh
Article No.: 57
DOI: 10.1145/2883609

The clock networks of many modern circuits have to operate in multiple corners and multiple modes (MCMM). We propose to construct mode-reconfigurable clock trees (MRCTs) based on mode separation and scenario compression. The technique of scenario...

A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition Using Wearables
Hassan Ghasemzadeh, Ramin Fallahzadeh, Roozbeh Jafari
Article No.: 58
DOI: 10.1145/2886096

Wearables are being widely utilized in health and wellness applications, primarily due to the recent advances in sensor and wireless communication, which enhance the promise of wearable systems in providing continuous and real-time monitoring and...

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
Article No.: 59
DOI: 10.1145/2890498

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of...

On Battery Recovery Effect in Wireless Sensor Nodes
Swaminathan Narayanaswamy, Steffen Schlueter, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Harry Ernst Hoster
Article No.: 60
DOI: 10.1145/2890501

With the perennial demand for longer runtime of battery-powered Wireless Sensor Nodes (WSNs), several techniques have been proposed to increase the battery runtime. One such class of techniques exploiting the battery recovery effect...

Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques
Dani Tannir, Ya Wang, Peng Li
Article No.: 61
DOI: 10.1145/2890500

The development of enhanced modeling techniques for the simulation of switched-mode Pulse Width Modulated (PWM) DC-DC power converters using circuit averaging is the main focus of this article. The circuit-averaging technique has traditionally...

Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs
Sebastian Steinhorst, Matthias Kauer, Arne Meeuw, Swaminathan Narayanaswamy, Martin Lukasiewycz, Samarjit Chakraborty
Article No.: 62
DOI: 10.1145/2891407

This article introduces a Cyber-physical Co-Simulation Framework (CPCSF) for design and analysis of smart cells that enable scalable battery pack and Battery Management System (BMS) architectures. In contrast to conventional cells in battery...

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs
Ujjwal Guin, Qihang Shi, Domenic Forte, Mark M. Tehranipoor
Article No.: 63
DOI: 10.1145/2893183

With the advent of globalization in the semiconductor industry, it is necessary to prevent unauthorized usage of third-party IPs (3PIPs), cloning and unwanted modification of 3PIPs, and unauthorized production of ICs. Due to the increasing...

Timing Path-Driven Cycle Cutting for Sequential Controllers
William Lee, Vikas S. Vij, Kenneth S. Stevens
Article No.: 64
DOI: 10.1145/2893473

Power and performance optimization of integrated circuits is performed by timing-driven algorithms that operate on directed acyclic graphs. Sequential circuits and circuits with topological feedback contain cycles. Cyclic circuits must be...

Hierarchical Statistical Leakage Analysis and Its Application
Yang Xu, Jürgen Teich
Article No.: 65
DOI: 10.1145/2896820

In this article, we investigate a hierarchical statistical leakage analysis (HSLA) design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power...

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient
Ramprasath S, Vinita Vasudevan
Article No.: 66
DOI: 10.1145/2896819

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based...

Ensemble Reduction via Logic Minimization
Hongfei Wang, R. D. (Shawn) Blanton
Article No.: 67
DOI: 10.1145/2897515

An ensemble of machine learning classifiers usually improves generalization performance and is useful for many applications. However, the extra memory storage and computational cost incurred from the combined models often limits their potential...

N-Detection Test Sets for Circuits with Multiple Independent Scan Chains
Irith Pomeranz
Article No.: 68
DOI: 10.1145/2897514

In a circuit with multiple independent scan chains, it is possible to operate groups of scan chains independently in functional or shift mode. This design-for-testability approach can be used to increase the quality of a test set. This article...

Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory
Jae-Yeon Won, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu
Article No.: 69
DOI: 10.1145/2897394

With the breakdown of Dennard’s scaling over the past decade, performance growth of modern microprocessor design has largely relied on scaling core count in chip multiprocessors (CMPs). The challenge of chip power density, however, remains...

Area-Aware Decomposition for Single-Electron Transistor Arrays
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan
Article No.: 70
DOI: 10.1145/2898998

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large...

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai (Helen) Li, Bingsheng He
Article No.: 71
DOI: 10.1145/2901295

While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly...

Index-Resilient Zero-Suppressed BDDs: Definition and Operations
Anna Bernasconi, Valentina Ciriani
Article No.: 72
DOI: 10.1145/2905363

Zero-Suppressed Binary Decision Diagrams (ZDDs) are widely used data structures for representing and handling combination sets and Boolean functions. In particular, ZDDs are commonly used in CAD for the synthesis and verification of integrated...