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Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors
Hai Wang, Jian Ma, Sheldon X.-D. Tan, Chi Zhang, He Tang, Keheng Huang, Zhenghong Zhang
Article No.: 1
It is challenging to manage the thermal behavior of many-core microprocessors while still keeping them running at high performance since the control complexity increases as the core number increases. In this article, a novel hierarchical dynamic...
Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip
Sudip Poddar, Sarmishtha Ghoshal, Krishnendu Chakrabarty, Bhargab B. Bhattacharya
Article No.: 2
Digital (droplet-based) microfluidic technology offers an attractive platform for implementing a wide variety of biochemical laboratory protocols, such as point-of-care diagnosis, DNA analysis, target detection, and drug discovery. A digital...
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers
Robert Czerwinski, Dariusz Kania
Article No.: 3
The logic synthesis of ultra-high-speed FSMs is presented. The state assignment is based on a well-known method that uses output vectors. This technique is adjusted to include elements of two-level minimization and takes into account the limited...
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture
Shirshendu Das, Hemangee K. Kapoor
Article No.: 4
Multicore processors have proliferated several domains ranging from small-scale embedded systems to large data centers, making tiled CMPs (TCMPs) the essential next-generation scalable architecture. NUCA architectures help in managing the capacity...
Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization
Yu-Wei Wu, Yiyu Shi, Sudip Roy, Tsung-Yi Ho
Article No.: 5
As finite energy resources are being consumed at faster rate than they can be replaced, renewable energy resources have drawn extensive attention. Wind power development is one such example growing significantly throughout the world. The main...
Given the increasing complexity of modern electronics and the cost of fabrication, entities from around the globe have become more heavily involved in all phases of the electronics supply chain. In this environment, hardware Trojans (i.e.,...
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests
Article No.: 7
This article describes a procedure for test data compression targeting functional and partially functional broadside tests. The scan-in state of such a test is either a reachable state or has a known Hamming distance from a reachable state....
Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor
Jinyong Lee, Ingoo Heo, Yongje Lee, Yunheung Paek
Article No.: 8
For decades, various concepts in security monitoring have been proposed. In principle, they all in common in regard to the monitoring of the execution behavior of a program (e.g., control-flow or dataflow) running on the machine to find symptoms...
Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling (WL) is an effective way to improve PCM endurance, but its major challenge is how to efficiently...
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement
Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young
Article No.: 10
Routability is one of the most important problems in high-performance circuit designs. From the viewpoint of placement design, two major factors cause routing congestion: (i) interconnections between cells and (ii) connections on macro blockages....
A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities
Bodhisatwa Mazumdar, Sk. Subidh Ali, Ozgur Sinanoglu
Article No.: 11
In this article, we present a compact implementation of the Salsa20 stream cipher that is targeted towards lightweight cryptographic devices such as radio-frequency identification (RFID) tags. The Salsa20 stream cipher, ann addition-rotation-XOR...
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures
Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen
Article No.: 12
Scratchpad memory (SPM) is considered a useful component in the memory hierarchy, solely or along with caches, for meeting the power and energy constraints as performance ceases to be the sole criteria for processor design. Although the efficiency...
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models
Hossein Mehri, Bijan Alizadeh
Article No.: 13
FPGA architectural optimization has emerged as one of the most important digital design challenges. In recent years, experimental methods have been replaced by analytical ones to find the optimized architecture. Time is the main reason for this...
Office machines (such as printers, scanners, facsimile machines, and copiers) can consume significant amounts of power. Most office machines have sleep modes to save power. Power management of these machines is usually timeout-based: a machine...
Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow
Joost-Pieter Katoen, Hao Wu
Article No.: 15
The Scenario-Aware Dataflow (SADF) model is based on concurrent actors that interact via channels. It combines streaming data and control to capture scenarios while incorporating hard and soft real-time aspects. To model data-flow computations...
Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction...
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection
Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi, Sreenivas Gangadhar
Article No.: 17
A Monte Carlo-based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths...
During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of nonvolatile flash in the system’s memory hierarchy. The increasing capacity of NAND flash memory introduces a large RAM footprint...
ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems
Piyoosh Purushothaman Nair, Arnab Sarkar, N. M. Harsha, Megha Gandhi, P. P. Chakrabarti, Sujoy Ghose
Article No.: 19
Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and quality-of-service guarantees on multiprocessors form an attractive alternative in real-time embedded systems that concurrently run a...