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Design Automation of Electronic Systems (TODAES)

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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 4 Issue 1, Jan. 1999

Bus-based communication synthesis on system level
Michael Gasteier, Manfred Glesner
Pages: 1-11
DOI: 10.1145/298865.298866
In this article, we present an approach to automatic generation of communication topologies for statically scheduled systems of subsystems. Given a specification containing a set of processes that communicate via abstract send and receive...

A text-compression-based method for code size minimization in embedded systems
Stan Liao, Srinivas Devadas, Kurt Keutzer
Pages: 12-38
DOI: 10.1145/298865.298867
We address the problem of code-size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systemswe use data-compression methods to develop code-size minimization...

On the crossing distribution problem
Xiaoyu Song, Yuke Wang
Pages: 39-51
DOI: 10.1145/298865.298868
VLSI layout design is typically decomposed into four steps: placement, global routing, routing region definition, and detailed routing. The crossing distribution problem occurs prior to detailed routing [Groenveld 1989;...

Two-level logic minimization for low power
Jyh-Mou Tseng, Jing-Yang Jou
Pages: 52-69
DOI: 10.1145/298865.298869
In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and...

Procedure cloning: a transformation for improved system-level functional partitioning
Frank Vahid
Pages: 70-96
DOI: 10.1145/298865.298871
Functional partitioning assigns the functions of a system's program-like specification among system components, such as standard-software and custom-hardware processors. We introduce a new transformation, called procedure cloning, that...

Power reduction and power-delay trade-offs using logic transformations
Qi Wang, Sarma B. K. Vrudhula, Gary Yeap, Shantanu Ganguly
Pages: 97-121
DOI: 10.1145/298865.298872
We present an efficient technique to reduce the switching activity in a technology-mapped CMOS combinational circuit based on local logic transformations. The transformations consist of adding redundant connections or gates so as to reduce...