Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section of IDEA: Integrating Dataflow, Embedded Computing, and Architecture, Volume 22 Issue 2, March 2017

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test
Phuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay
Article No.: 20
DOI: 10.1145/2940326

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In the existing literature on PUFs,...

CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks
Di Zhu, Siyu Yue, Massoud Pedram, Lizhong Chen
Article No.: 21
DOI: 10.1145/2950045

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), on-chip networks are facing serious challenges in providing fast communication among various tasks and cores. One promising on-chip network design approach shown in recent...

Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis
Mohammad Reza Azarbad, Bijan Alizadeh
Article No.: 22
DOI: 10.1145/2953879

In this article, we present a novel methodology based on SMT-solvers to verify equality of a high-level described specification and a pipelined RTL implementation produced by a high-level synthesis tool. The complex transformations existing in the...

Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models
Qingling Zhao, Zaid Al-Bayati, Zonghua Gu, Haibo Zeng
Article No.: 23
DOI: 10.1145/2968445

Model-based design using Synchronous Reactive (SR) models enables early design and verification of application functionality in a platform-independent manner, and the implementation on the target platform should guarantee the preservation of...

Reducing the Complexity of Dataflow Graphs Using Slack-Based Merging
Hazem Ismail Ali, Sander Stuijk, Benny Akesson, Luís Miguel Pinho
Article No.: 24
DOI: 10.1145/2956232

There exist many dataflow applications with timing constraints that require real-time guarantees on safe execution without violating their deadlines. Extraction of timing parameters (offsets, deadlines, periods) from these applications enables the...

Security in Automotive Networks: Lightweight Authentication and Authorization
Philipp Mundhenk, Andrew Paverd, Artur Mrowca, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty
Article No.: 25
DOI: 10.1145/2960407

With the increasing amount of interconnections between vehicles, the attack surface of internal vehicle networks is rising steeply. Although these networks are shielded against external attacks, they often do not have any internal security to...

On the Restore Time Variations of Future DRAM Memory
Xianwei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang
Article No.: 26
DOI: 10.1145/2967609

As the de facto main memory standard, DRAM (Dynamic Random Access Memory) has achieved dramatic density improvement in the past four decades, along with the advancements in process technology. Recent studies reveal that one of the major...

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration
Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang
Article No.: 27
DOI: 10.1145/2979143

Flash memory is widely used in mobile phones to store contact information, application files, and other types of data. In an operating system, the buffer cache keeps the I/O blocks in dynamic random access memory (DRAM) to reduce the slow flash...

An Elastic Mixed-Criticality Task Model and Early-Release EDF Scheduling Algorithms
Hang Su, Dakai Zhu, Scott Brandt
Article No.: 28
DOI: 10.1145/2984633

Many algorithms have recently been studied for scheduling mixed-criticality (MC) tasks. However, most existing MC scheduling algorithms guarantee the timely executions of high-criticality (HC) tasks at the expense of discarding low-criticality...

Computation of Seeds for LFSR-Based n-Detection Test Generation
Irith Pomeranz
Article No.: 29
DOI: 10.1145/2994144

This article describes a new procedure that generates seeds for LFSR-based test generation when the goal is to produce an n-detection test set. The procedure does not use test cubes in order to avoid the situation where a seed does...

Scale & Cap: Scaling-Aware Resource Management for Consolidated Multi-threaded Applications
Can Hankendi, Ayse Kivilcim Coskun
Article No.: 30
DOI: 10.1145/2994145

As the number of cores per server node increases, designing multi-threaded applications has become essential to efficiently utilize the available hardware parallelism. Many application domains have started to adopt multi-threaded programming;...

Secure and Flexible Trace-Based Debugging of Systems-on-Chip
Jerry Backer, David Hely, Ramesh Karri
Article No.: 31
DOI: 10.1145/2994601

This work tackles the conflict between enforcing security of a system-on-chip (SoC) and providing observability during trace-based debugging. On one hand, security objectives require that assets remain confidential at different stages of the SoC...

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors
Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor
Article No.: 32
DOI: 10.1145/2996182

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction...

Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices
Rui Santos, Shyamsundar Venkataraman, Akash Kumar
Article No.: 33
DOI: 10.1145/2997646

Commercial off-the-shelf (COTS) reconfigurable devices have been recognized as one of the most suitable processing devices to be applied in nano-satellites, since they can satisfy and combine their most important requirements, namely processing...

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems
Andrea Enrici, Ludovic Apvrille, Renaud Pacalet
Article No.: 34
DOI: 10.1145/2999537

In Model-Driven Engineering system-level approaches, the design of communication protocols and patterns is subject to the design of processing operations (computations) and to their mapping onto execution resources. However, this strategy allows...

Section: Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Special Section: Integrating Dataflow, Embedded Computing and Architecture
Twan Basten, Orlando Moreira, Robert de Groote
Article No.: 35
DOI: 10.1145/3023455

Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks
Junchul Choi, Soonhoi Ha
Article No.: 36
DOI: 10.1145/2997644

In this article, we propose a novel technique that estimates a tight upper bound of the worst-case response time (WCRT) of a synchronous dataflow (SDF) graph when the SDF graph shares processors with other real-time tasks. When an SDF graph is...

Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay
Hanwoong Jung, Hyunok Oh, Soonhoi Ha
Article No.: 37
DOI: 10.1145/2997645

The Synchronous Data Flow (SDF) model is widely used for specifying signal processing or streaming applications. Since modern embedded applications become more complex with dynamic behavior changes at runtime, several extensions of the SDF model...

A Survey of Parametric Dataflow Models of Computation
Adnan Bouakaz, Pascal Fradet, Alain Girault
Article No.: 38
DOI: 10.1145/2999539

Dataflow models of computation (MoCs) are widely used to design embedded signal processing and streaming systems. Dozens of dataflow MoCs have been proposed in the past few decades. More recently, several parametric dataflow MoCs have been...

Symbolic Analyses of Dataflow Graphs
Adnan Bouakaz, Pascal Fradet, Alain Girault
Article No.: 39
DOI: 10.1145/3007898

The synchronous dataflow model of computation is widely used to design embedded stream-processing applications under strict quality-of-service requirements (e.g., buffering size, throughput, input-output latency). The required analyses can either...