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Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms
Kaige Yan, Lu Peng, Mingsong Chen, Xin Fu
Article No.: 58
Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, energy-efficient computing is highly desired. In this article, we focus on energy-efficient cache design in...
Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors
Taehyun Kim, Jongbum Lim, Jinku Kim, Woo-Cheol Cho, Eui-Young Chung, Hyuk-Jun Lee
Article No.: 59
Scalability of network processor-based routers heavily depends on limitations imposed by memory accesses and associated power consumption. Bandwidth shaping of a flow is a key function, which requires a token bucket per output queue and abuses...
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction
Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath
Article No.: 60
A large semiconductor product company spends hundreds of millions of dollars each year on design infrastructure to meet tapeout schedules for multiple concurrent projects. Resources (servers, electronic design automation tool licenses, engineers,...
Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a...
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes
Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg
Article No.: 62
Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply...
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip
Katherine Shu-Min Li, Sying-Jyan Wang
Article No.: 63
A systematic design methodology is presented for custom Network-on-Chip (NoC) in three-dimensional integrated circuits (3D-ICs). In addition, fault tolerance is supported in the NoC if extra links are included in the NoC topology. In the proposed...
Approximate Energy-Efficient Encoding for Serial Interfaces
Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino
Article No.: 64
Serial buses are ubiquitous interconnections in embedded computing systems that are used to interface processing elements with peripherals, such as sensors, actuators, and I/O controllers. Despite their limited wiring, as off-chip connections they...
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies
Benjamin Carrion Schafer
Article No.: 65
This works presents a Design Space Exploration (DSE) method for Behavioral IPs (BIPs) given in ANSI-C or SystemC to find the smallest micro-architecture for a specific target latency. Previous work on High-Level Synthesis (HLS) DSE mainly focused...
Generating Current Constraints to Guarantee RLC Power Grid Safety
Zahi Moudallal, Farid N. Najm
Article No.: 66
A critical task during early chip design is the efficient verification of the chip power distribution network. Vectorless verification, developed since the mid-2000s as an alternative to traditional simulation-based methods, requires the user to...
Test Modification for Reduced Volumes of Fail Data
Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman
Article No.: 67
As part of a yield improvement process, fail data is collected from faulty units. Several approaches exist for reducing the tester time and the volume of fail data that needs to be collected based on the observation that a subset of the fail data...
Small-signal models of pulse-width modulation (PWM) converters are widely used for analyzing stability and play an important role in converter design and control. However, existing small-signal models either are based on averaged DC behaviors, and...
Training Fixed-Point Classifiers for On-Chip Low-Power Implementation
Hassan Albalawi, Yuanning Li, Xin Li
Article No.: 69
In this article, we develop several novel algorithms to train classifiers that can be implemented on chip with low-power fixed-point arithmetic with extremely small word length. These algorithms are based on Linear Discriminant Analysis (LDA),...
Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era
Mohaddeseh Hoveida, Fatemeh Aghaaliakbari, Ramin Bashizade, Mohammad Arjomand, Hamid Sarbazi-Azad
Article No.: 70
The failure of Dennard scaling has led to the utilization wall that is the source of dark silicon and limits the percentage of a chip that can actively switch within a given power budget. To address this issue, a structure is needed to guarantee...
Spatio-Temporal Scheduling of Preemptive Real-Time Tasks on Partially Reconfigurable Systems
Sangeet Saha, Arnab Sarkar, Amlan Chakrabarti
Article No.: 71
Reconfigurable devices that promise to offer the twin benefits of flexibility as in general-purpose processors along with the efficiency of dedicated hardwares often provide a lucrative solution for many of today’s highly complex real-time...
Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation
Jaume Abella, Maria Padilla, Joan Del Castillo, Francisco J. Cazorla
Article No.: 72
Extreme Value Theory (EVT) has been historically used in domains such as finance and hydrology to model worst-case events (e.g., major stock market incidences). EVT takes as input a sample of the distribution of the variable to model and fits the...
Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article...
Time-Triggered Scheduling of Mixed-Criticality Systems
Lalatendu Behera, Purandar Bhaduri
Article No.: 74
Real-time and embedded systems are moving from the traditional design paradigm to integration of multiple functionalities onto a single computing platform. Some of the functionalities are safety critical and subject to certification. The rest of...
Incremental Layer Assignment for Timing Optimization
Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
Article No.: 75
With VLSI technology nodes scaling into the nanometer regime, interconnect delay plays an increasingly critical role in timing. For layer assignment, most works deal with via counts or total net delays, ignoring critical paths of each net and...