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Optimization and Quality Estimation of Circuit Design via Random Region Covering Method
Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng
Article No.: 1
Random region covering is a global optimization technique that explores the landscape by introducing multiple random starting points to initiate the local optimization solvers. This study applies the random region covering technique to circuit...
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources
Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, Tm Mak, Jennifer Kitchen, Sule Ozev
Article No.: 2
This article presents a Built-in self-test (BIST) solution for polar transceivers with low cost and high accuracy. Radio frequency (RF) Polar transceivers are desirable for portable devices due to higher power efficiency compared to traditional RF...
Electric Vehicle Optimized Charge and Drive Management
Korosh Vatanparvar, Mohammad Abdullah Al Faruque
Article No.: 3
Electric vehicles (EVs) have been considered as a solution to the environmental issues caused by transportation, such as air pollution and greenhouse gas emission. However, limited energy capacity, scarce EV supercharging stations, and long...
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong
Article No.: 4
Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging...
Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing
A. Satya Trinadh, Seetal Potluri, Sobhan Babu Ch., V. Kamakoti, Shiv Govind Singh
Article No.: 5
Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural...
Two-Stage Layout Decomposition for Hybrid E-Beam and Triple Patterning Lithography
Xingquan Li, Wenxing Zhu
Article No.: 6
Hybrid e-beam lithography (EBL) and triple patterning lithography (TPL) are advanced technologies for the manufacture of integrated circuits. We propose a technology that combines the advantages of EBL and TPL, which is more promising for the...
VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs
Sourav Das, Dongjin Lee, Wonje Choi, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
Article No.: 7
The emergence of 3D network-on-chip (NoC) has revolutionized the design of high-performance and energy-efficient manycore chips. However, the anticipated performance gain can be compromised due to the degradation and failure of vertical links...
A Novel Range Matching Architecture for Packet Classification Without Rule Expansion
Shanmugakumar Murugesan, Noor Mahammad Sk
Article No.: 8
The speed requirement for the routing table lookup and the packet classification is rapidly increasing due to the increase in the number of packets needed to be processed per second. The hardware-based packet classification relies on ternary...
A Hierarchical Technique for Statistical Path Selection and Criticality Computation
P. R. Chithira, Vinita Vasudevan
Article No.: 9
Due to process variations, every path in the circuit is associated with a probability of being critical and a measure of this probability is the criticality of the path. Identification of critical paths usually proceeds in two steps, namely,...
Architectural Supports to Protect OS Kernels from Code-Injection Attacks and Their Applications
Hyungon Moon, Jinyong Lee, Dongil Hwang, Seonhwa Jung, Jiwon Seo, Yunheung Paek
Article No.: 10
The kernel code injection is a common behavior of kernel-compromising attacks where the attackers aim to gain their goals by manipulating an OS kernel. Several security mechanisms have been proposed to mitigate such threats, but they all suffer...
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
Article No.: 11
Directed self-assembly (DSA) complemented with multiple patterning (MP) is an attractive next generation lithography (NGL) technique for contact-hole generation. Nevertheless, a high-quality DSA-aware layout decomposer is required to enable the...
An Adaptive Markov Model for the Timing Analysis of Probabilistic Caches
Chao Chen, Giovanni Beltrame
Article No.: 12
Accurate timing prediction for real-time embedded software execution is becoming a problem due to the increasing complexity of computer architecture, and the presence of mixed-criticality workloads. Probabilistic caches were proposed to set bounds...