Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23 Issue 2, November 2017

DYNASCORE: DYNAmic Software COntroller to Increase REsource Utilization in Mixed-Critical Systems
Angeliki Kritikakou, Thibaut Marty, Matthieu Roy
Article No.: 13
DOI: 10.1145/3110222

In real-time mixed-critical systems, Worst-Case Execution Time (WCET) analysis is required to guarantee that timing constraints are respected—at least for high-criticality tasks. However, the WCET is pessimistic compared to the real...

Emerging NVM: A Survey on Architectural Integration and Research Challenges
Jalil Boukhobza, Stéphane Rubini, Renhai Chen, Zili Shao
Article No.: 14
DOI: 10.1145/3131848

There has been a surge of interest in Non-Volatile Memory (NVM) in recent years. With many advantages, such as density and power consumption, NVM is carving out a place in the memory hierarchy and may eventually change our view of computer...

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs
Congming Gao, Liang Shi, Yejia Di, Qiao Li, Chun Jason Xue, Kaijie Wu, Edwin Sha
Article No.: 15
DOI: 10.1145/3131850

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear...

Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing
Jaeyung Jun, Kyu Hyun Choi, Hokwon Kim, Sang Ho Yu, Seon Wook Kim, Youngsun Han
Article No.: 16
DOI: 10.1145/3131241

Recently, scaling down dynamic random access memory (DRAM) has become more of a challenge, with more faults than before and a significant degradation in yield. To improve the yield in DRAM, a redundancy repair technique with intra-subarray...

Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits
Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
Article No.: 17
DOI: 10.1145/3131849

The exponential increase in scale and complexity of very large-scale integrated circuits (VLSIs) poses a great challenge to current electronic design automation (EDA) techniques. As an essential step in the whole EDA layout synthesis, placement is...

Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files
Shao-Chung Wang, Li-Chen Kan, Chao-Lin Lee, Yuan-Shin Hwang, Jenq-Kuen Lee
Article No.: 18
DOI: 10.1145/3133218

A modern GPU can simultaneously process thousands of hardware threads. These threads are grouped into fixed-size SIMD batches executing the same instruction on vectors of data in a lockstep to achieve high throughput and performance. The register...

C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency
Chen-Hsuan Lin, Lu Wan, Deming Chen
Article No.: 20
DOI: 10.1145/3144534

The better-than-worst-case (BTW) design methodology can achieve higher circuit energy efficiency, performance, or reliability by allowing timing errors for rare cases and rectifying them with error correction mechanisms. Therefore, the performance...

Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms
Kathrin Rosvall, Ingo Sander
Article No.: 21
DOI: 10.1145/3133210

Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches...

Multi-Objective 3D Floorplanning with Integrated Voltage Assignment
Johann Knechtel, Jens Lienig, Ibrahim (Abe) M. Elfadel
Article No.: 22
DOI: 10.1145/3149817

Voltage assignment is a well-known technique for circuit design, which has been applied successfully to reduce power consumption in classical 2D integrated circuits (ICs). Its usage in the context of 3D ICs has not been fully explored yet although...