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Design Automation of Electronic Systems (TODAES)

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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 5 Issue 1, Jan. 2000

A code-motion pruning technique for global scheduling
Luiz C. V. Dos Santos, M. J. M. Heijligers, C. A. J. Van Eijk, J. Van Eijnhoven, J. A. G. Jess
Pages: 1-38
DOI: 10.1145/329458.329461
In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditionals in the behavioral description represents an obstacle to exploit parallelism. Most existing methods use greedy choices in such a way that the...

Multiway FPGA partitioning by fully exploiting design hierarchy
Wen-Jong Fang, Allen C.-H. Wu
Pages: 34-50
DOI: 10.1145/329458.329463
In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a...

CMAPS: a cosynthesis methodology for application-oriented parallel systems
Pao-Ann Hsiung
Pages: 51-81
DOI: 10.1145/329458.329465
Currently, a lot of research is devoted to system design, and little work is done on requirements analysis. Besides going from specification to design, one of our main objectives is to show how an application...

On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs
Dinesh P. Mehta, Naveed Sherwani
Pages: 82-97
DOI: 10.1145/329458.329470
This paper presents three minimum-area floorplanning algorithms that use flexible arbitrary rectilinear shapes for the standard cell regions in MBC design. The first algorithm (pure HCST) introduces a grid traversal technique which guarantees a...

Power-delay optimizations in gate sizing
Sachin S. Sapatnekar, Weitong Chuang
Pages: 98-114
DOI: 10.1145/329458.329473
The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modeling technique is used to calculate the short-circuit...