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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 6 Issue 2, April 2001

Data and memory optimization techniques for embedded systems
P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, P. G. Kjeldsberg
Pages: 149-206
DOI: 10.1145/375977.375978
We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of...

An algorithm for synthesis of large time-constrained heterogeneous adaptive systems

Pages: 207-225
DOI: 10.1145/375977.375979
Large time-constrained applications are highly computer-intensive and are often implemented as a complex organization of pipelined data parallel tasks on a pool of embedded processors, DSP processors, and FPGAs. The large number of design...

Intrinsic response for analog module testing using an analog testability bus
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
Pages: 226-243
DOI: 10.1145/375977.375981
A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test...

Verifying sequential equivalence using ATPG techniques
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
Pages: 244-275
DOI: 10.1145/375977.376022
In this paper we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even...