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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 6 Issue 3, July 2001

Processor modeling and code selection for retargetable compilation
J. Van Praet, D. Lanneer, W. Geurts, G. Goossens
Pages: 277-307
DOI: 10.1145/383251.383252
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To...

Von Neumann hybrid cellular automata for generating deterministic test sequences
D. Kagaris, S. Tragoudas
Pages: 308-321
DOI: 10.1145/383251.383254
We propose an on-chip test pattern generator that uses an one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first...

Constrained polygon transformations for incremental floorplanning
Swanwa Liao, Mario A. Lopez, Dinesh Mehta
Pages: 322-342
DOI: 10.1145/383251.383255
A productivity-driven methodology for incremental floorplanning is described and the constrained polygon transformation problem, a key step of this methodology, is formulated. The input to the problem consists of a floorplan...

Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
Chris Chu, D. F. Wong
Pages: 343-371
DOI: 10.1145/383251.383256
In this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three cases, namely using no buffer (i.e., wire sizing alone), using a...

Efficient list-approximation techniques for floorplan area minimization
Xiaobo Sharon Hu, Danny Z. Chen, Rajeshkumar Sambandam
Pages: 372-400
DOI: 10.1145/383251.383257
As the sizes of many IC design problems become increasingly larger, approximation has become a valuable approach for arriving at satisfactory results without incurring exorbitant computational cost. In this paper, we present several...

Integrated test of interacting controllers and datapaths
Mehrdad Nourani, Joan Carletta, Christos Papachristou
Pages: 401-422
DOI: 10.1145/383251.383258
In systems consisting of interacting datapaths and controllers and utilizing built-in self test (BIST), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during...

Introducing redundant computations in RTL data paths for reducing BIST resources
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Pages: 423-445
DOI: 10.1145/383251.383253
The need for considering BIST requirements during the scheduling and assignment stages of behavioral synthesis has been demonstrated in previous research and techniques for reducing BIST resources of a data path during these stages of synthesis...