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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 6 Issue 4, October 2001

Slicible rectangular graphs and their optimal floorplans

Pages: 447-470
DOI: 10.1145/502175.502176
Rectangular dualization method of floorplanning usually involves topology generation followed by sizing. Slicible topologies are often preferred for their simplicity and efficiency. While slicible topologies can be obtained efficiently, existing...

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists
Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty
Pages: 471-489
DOI: 10.1145/502175.502177
This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the...

A fast approach to computing exact solutions to the resource-constrained scheduling problem
M. Narasimhan, J. Ramanujam
Pages: 490-500
DOI: 10.1145/502175.502178
This article presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branch-and-bound search...

Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs
Ramesh Karri, Balakrishnan Iyer
Pages: 501-515
DOI: 10.1145/502175.502179
We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection. Introspection uses idle computation cyles in the data path and idle data transfer cycles in the...

Optimal design of synchronous circuits using software pipelining techniques
François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer
Pages: 516-532
DOI: 10.1145/502175.502180
We present a method to optimize clocked circuits by relocating and changing the time of activation of registers to maximize the throughput. Our method is based on a modulo scheduling algorithm for software pipelining, instead of retiming. It...

On the fundamental limitations of transformational design
Jeroen Voeten
Pages: 533-552
DOI: 10.1145/502175.502181
The completeness of a collection of design transformations is an important aspect in transformational design. Completeness guarantees that any correct design can in principle be explored using the transformation system. In the field of...

Data memory design and exploration for low-power embedded systems

Pages: 553-568
DOI: 10.1145/502175.502182
In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration procedure based on three performance metrics, namely,...

Using complete-1-distinguishability for FSM equivalence checking
Pranav Ashar, Aarti Gupta, Sharad Malik
Pages: 569-590
DOI: 10.1145/502175.502183
This article introduces the notion of a Complete-1-Distinguishability (C-1-D) property for simplifying equivalence checking of finite state machines (FSMs). When a specification machine has the C-1-D property, the traversal of the product machine can...

Optimizing designs containing black boxes
Tai-Hung Liu, Adnan Aziz, Vigyan Singhal
Pages: 591-601
DOI: 10.1145/502175.502184
We are concerned with optimizing gate-level netlists containing "e;black boxes,"e; that is, components whose functionality is not available to the optimization tool. We establish a notion of equivalence for gate-level netlists containing...

Forced simulation: A technique for automating component reuse in embedded systems
Partha S. Roop, A. Sowmya, S. Ramesh
Pages: 602-628
DOI: 10.1145/502175.502185
Component reuse techniques have been a recent focus of research because they are seen as the next-generation techniques to handle increasing system complexities. However, there are several unresolved issues to be addressed and prominent among them is...

An exact solution to the minimum size test pattern problem
Paulo F. Flores, Horácio C. Neto, João P. Marques-Silva
Pages: 629-644
DOI: 10.1145/502175.502186
This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different...