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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 7 Issue 3, July 2002

UST/DME: a clock tree router for general skew constraints
Chung-wen Albert Tsao, Cheng-kok Koh
Pages: 359-379
DOI: 10.1145/567270.567271
In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the...

Efficient scheduling of conditional behaviors for high-level synthesis
Apostolos A. Kountouris, Christophe Wolinski
Pages: 380-412
DOI: 10.1145/567270.567272
As hardware designs get increasingly complex and time-to-market constraints get tighter there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both dataflow-dominated and controlflow-dominated designs as well as...

Partitioning sequential programs for CAD using a three-step approach
Frank Vahid
Pages: 413-429
DOI: 10.1145/567270.567273
Many computer-aided design problems involve solutions that require the partitioning of a large sequential program written in a language such as C or VHDL. Such partitioning can improve design metrics such as performance, power, energy, size,...

Cluster assignment for high-performance embedded VLIW processors
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo A. De Veciana
Pages: 430-454
DOI: 10.1145/567270.567274
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with a large number of register file ports. Efficient utilization of a clustered datapath requires careful...

Estimation of state line statistics in sequential circuits
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
Pages: 455-473
DOI: 10.1145/567270.567275
In this article, we present a simulation-based technique for estimation of signal statistics (switching activity and signal probability) at the flip-flop output nodes (state signals) of a general sequential circuit. Apart from providing an estimate...

False-noise analysis using logic implications

Pages: 474-498
DOI: 10.1145/567270.567276
Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the...