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UST/DME: a clock tree router for general skew constraints
Chung-wen Albert Tsao, Cheng-kok Koh
In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the...
Efficient scheduling of conditional behaviors for high-level synthesis
Apostolos A. Kountouris, Christophe Wolinski
As hardware designs get increasingly complex and time-to-market constraints get tighter there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both dataflow-dominated and controlflow-dominated designs as well as...
Partitioning sequential programs for CAD using a three-step approach
Many computer-aided design problems involve solutions that require the partitioning of a large sequential program written in a language such as C or VHDL. Such partitioning can improve design metrics such as performance, power, energy, size,...
Cluster assignment for high-performance embedded VLIW processors
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo A. De Veciana
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with a large number of register file ports. Efficient utilization of a clustered datapath requires careful...
Estimation of state line statistics in sequential circuits
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
In this article, we present a simulation-based technique for estimation of signal statistics (switching activity and signal probability) at the flip-flop output nodes (state signals) of a general sequential circuit. Apart from providing an estimate...
False-noise analysis using logic implications
Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the...