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BDD-based logic synthesis for LUT-based FPGAs
Navin Vemuri, Priyank Kalla, Russell Tessier
Contemporary FPGA synthesis is a multiphase process that involves technology-independent logic optimization followed by FPGA-specific mapping to a target FPGA technology. Conventional technology-independent transformations target standard cells and...
Reduction design for generic universal switch blocks
Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong
A k-side switch block with W terminals per side is said to be a universal switch block ((k, W)-USB) if every set of the nets satisfying the routing constraint (i.e., the number of nets on each side is at most W) is...
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
Andreas Dandalis, Viktor K. Prasanna
FPGAs are a promising technology for accelerating SAT solvers. Besides their high density, fine granularity, and massive parallelism, FPGAs provide the opportunity for run-time customization of the hardware based on the given SAT instance. In this...
Behavioral synthesis of field programmable analog array circuits
Haibo Wang, Sarma B. K. Vrudhula
This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis,...
Instruction generation for hybrid reconfigurable systems
R. Kastner, A. Kaplan, S. Ogrenci Memik, E. Bozorgzadeh
Future computing systems need to balance flexibility, specialization, and performance in order to meet market demands and the computing power required by new applications. Instruction generation is a vital component for determining these trade-offs....
Performance-driven placement for dynamically reconfigurable FPGAs
Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For...
Efficient circuit clustering for area and power reduction in FPGAs
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
We utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits in clustered Field Programmable Gate Arrays (FPGAs). We show that careful matching of resource availability and design complexity during the clustering...
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
Shantanu Dutt, Vinay Verma, Hasan Arslan
Incremental physical CAD is encountered frequently in the so-called engineering change order (ECO) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the...